Voltage Monitoring 2 Circuit Control Register 0 (Lvd2Cr0) - Renesas RX100 Series User Manual

RX13T Group
8.2.8

Voltage Monitoring 2 Circuit Control Register 0 (LVD2CR0)

Address(es): 0008 C29Bh
b7 b6
LVD2R
LVD2RI
N
1 0
Value after reset:
x: Undefined
Bit Symbol Bit Name
b0 LVD2RIE Voltage Monitoring 2 Interrupt/Reset
Enable
b1 — Reserved
b2 LVD2CMPE Voltage Monitoring 2 Circuit
Comparison Result Output Enable
b3 — Reserved
b5, b4 — Reserved
b6 LVD2RI Voltage Monitoring 2 Circuit Mode
Select
b7 LVD2RN Voltage Monitoring 2 Reset Negation
Select
Note: Set the PRCR.PRC3 bit to 1 (write enabled) before rewriting this register.
LVD2RIE Bit (Voltage Monitoring 2 Interrupt/Reset Enable)
The LVD2RIE bit is enabled when the LVCMPCR.LVD2E bit is set to 1 (voltage detection 2 circuit enabled) and the
LVD2CMPE bit is set to 1 (voltage monitoring 2 circuit comparison results output enabled).
Ensure that neither a voltage monitoring 2 reset nor a voltage monitoring 2 non-maskable interrupt is generated during
programming or erasure of the flash memory.
LVD2RN Bit (Voltage Monitoring 2 Reset Negation Select)
If the LVD2RN bit is to be set to 1 (negation follows a stabilization time after assertion of the voltage monitoring 2 reset),
set the LOCOCR.LCSTP bit to 0 (LOCO is operating). Furthermore, if a transition to software standby mode, the only
possible value for the LVD2RN bit is 0 (negation follows a stabilization time after VCC > Vdet2 is detected). Do not set
the LVD2RN bit to 1 (negation follows a stabilization time after assertion of the voltage monitoring 2 reset).
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b5 b4 b3 b2
LVD2C
— — —
MPE
0 0 X 0
b1 b0
LVD2RI
—
E
0 0
Description
0: Disabled
1: Enabled
This bit is read as 0. The write value should be 0.
0: Voltage monitoring 2 circuit comparison results output
disabled
1: Voltage monitoring 2 circuit comparison results output
enabled
The read value is undefined. The write value should be 0.
These bits are read as 0. The write value should be 0.
0: Voltage monitoring 2 interrupt during Vdet2 passage
1: Voltage monitoring 2 reset enabled when the voltage
falls to and below Vdet2
0: Negation follows a stabilization time (tLVD2) after VCC
> Vdet2 is detected.
1: Negation follows a stabilization time (tLVD2) after
assertion of the voltage monitoring 2 reset.
8. Voltage Detection Circuit (LVDAb)
Page 122 of 1041
R/W
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