C Status Register (Sisr) - Renesas RX100 Series User Manual

RX13T Group
2
23.2.18 I

C Status Register (SISR)

Address(es): SCI1.SISR 0008 A02Ch, SCI5.SISR 0008 A0ACh, SCI12.SISR 0008 B30Ch
b7 b6
— —
0 0
Value after reset:
x: Undefined
Bit Symbol Bit Name
b0 IICACKR ACK Reception Data Flag
b1 — Reserved
b2 — Reserved
b3 — Reserved
b5, b4 — Reserved
b7, b6 — Reserved
Note 1. Only 0 can be written to this bit, to clear the flag.
SISR is used to monitor state in relation to simple I
IICACKR Flag (ACK Reception Data Flag)
Received ACK and NACK bits can be read from this bit.
The IICACKR flag is updated at the rising of SSCLn clock for the ACK/NACK receiving bit.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b5 b4 b3 b2
— — — —
x x 0 x
Description
0: ACK received
1: NACK received
This bit is read as 0. The write value should be 0.
The read value is undefined.
This bit is read as 0. The write value should be 0.
The read value is undefined.
These bits are read as 0. The write value should be 0.
2
C mode.
23. Serial Communications Interface (SCIg, SCIh)
b1 b0
IICACK
—
R
0 0
R/W
1
R/W*
R/W
R
R/W
R
R/W
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