Port Output Enable Control Register 1 (Poecr1) - Renesas RX100 Series User Manual

RX13T Group
20.2.8

Port Output Enable Control Register 1 (POECR1)

Address(es): POE.POECR1 0008 C4CBh
b7 b6
MTU0D MTU0C
1ZE 1ZE
0 0
Value after reset:
Bit Symbol
b0 MTU0AZE
b1 MTU0BZE
b2 MTU0CZE
b3 MTU0DZE
b4 MTU0A1ZE
b5 MTU0B1ZE
b6 MTU0C1ZE
b7 MTU0D1ZE
Note 1. Can be modified only once after a reset.
The POECR1 register controls high-impedance state of the MTU0 pins.
MTU0AZE Bit (MTIOC0A (PB3) Pin High-Impedance Enable)
This bit specifies whether to switch the MTIOC0A output of PB3 to the high-impedance state when any of the
ICSR3.POE8F flag, SPOER.MTUCH0HIZ bit, and ICSR6.OSTSTF flag (when the OSTSTE bit is 1), or, as additionally
specified in the POECR5 register, the ICSRn.POEmF flag (n = 1, 4; m = 0, 10), or POECMPFR.CnFLAG flag (n = 0 to
2), is set to 1.
MTU0BZE Bit (MTIOC0B (PB2) Pin High-Impedance Enable)
This bit specifies whether to switch the MTIOC0B output of PB2 to the high-impedance state when any of the
ICSR3.POE8F flag, SPOER.MTUCH0HIZ bit, and ICSR6.OSTSTF flag (when the OSTSTE bit is 1), or, as additionally
specified in the POECR5 register, the ICSRn.POEmF flag (n = 1, 4; m = 0, 10), or POECMPFR.CnFLAG flag (n = 0 to
2), is set to 1.
MTU0CZE Bit (MTIOC0C (PB1) Pin High-Impedance Enable)
This bit specifies whether to switch the MTIOC0C output of PB1 to the high-impedance state when any of the
ICSR3.POE8F flag, SPOER.MTUCH0HIZ bit, and ICSR6.OSTSTF flag (when the OSTSTE bit is 1), or, as additionally
specified in the POECR5 register, the ICSRn.POEmF flag (n = 1, 4; m = 0, 10), or POECMPFR.CnFLAG flag (n = 0 to
2), is set to 1.
MTU0DZE Bit (MTIOC0D (PB0) Pin High-Impedance Enable)
This bit specifies whether to switch the MTIOC0D output of PB0 to the high-impedance state when any of the
ICSR3.POE8F flag, SPOER.MTUCH0HIZ bit, and ICSR6.OSTSTF flag (when the OSTSTE bit is 1), or, as additionally
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b5 b4 b3 b2
MTU0B MTU0A MTU0D MTU0C
1ZE 1ZE ZE ZE
0 0 0 0
Bit Name
MTIOC0A (PB3) Pin High-Impedance
Enable
MTIOC0B (PB2) Pin High-Impedance
Enable
MTIOC0C (PB1) Pin High-Impedance
Enable
MTIOC0D (PB0) Pin High-Impedance
Enable
MTIOC0A (PD3) Pin High-Impedance
Enable
MTIOC0B (PD4) Pin High-Impedance
Enable
MTIOC0C (PD5) Pin High-Impedance
Enable
MTIOC0D (PD6) Pin High-Impedance
Enable
b1 b0
MTU0B MTU0A
ZE ZE
0 0
Description
0: Does not switch the pin to high-impedance state.
1: Switch the pin to high-impedance state.
0: Does not switch the pin to high-impedance state.
1: Switch the pin to high-impedance state.
0: Does not switch the pin to high-impedance state.
1: Switch the pin to high-impedance state.
0: Does not switch the pin to high-impedance state.
1: Switch the pin to high-impedance state.
0: Does not switch the pin to high-impedance state.
1: Switch the pin to high-impedance state.
0: Does not switch the pin to high-impedance state.
1: Switch the pin to high-impedance state.
0: Does not switch the pin to high-impedance state.
1: Switch the pin to high-impedance state.
0: Does not switch the pin to high-impedance state.
1: Switch the pin to high-impedance state.
20. Port Output Enable 3 (POE3C)
Page 538 of 1041
R/W
1
R/W*
1
R/W*
R/W* 1
1
R/W*
1
R/W*
1
R/W*
1
R/W*
1
R/W*