Operation - Renesas RX100 Series User Manual

RX13T Group
20.3

Operation

The following shows the target pins and conditions for high-impedance control.
(1) MTU3 pins (MTIOC3B, MTIOC3D)
When one of the following conditions is satisfied while the POECR2.MTU3BDZE bit is 1, the pins become high-
impedance.
 Operation for detection of the POE0# input level
When the ICSR1.POE0F flag becomes 1.
 Operation for comparison of the output levels on the MTIOC3B and MTIOC3D pins
When the OCSR1.OSF1 flag becomes 1 while the OCSR1.OCE1 bit is 1.
 SPOER setting
When the SPOER.MTUCH34HIZ bit is set to 1.
 Conditions added by POECR4
When the ICSR3.POE8F flag becomes 1 while the POECR4.IC3ADDMT34ZE bit and the ICSR3.POE8E bit are 1.
When the ICSR4.POE10F flag becomes 1 while the POECR4.IC4ADDMT34ZE bit and the ICSR4.POE10E bit are
1.
 Comparator output detection
When the POECMPFR.C0FLAG flag becomes 1 while the POECR4.CMADDMT34ZE bit is 1 and the
POECMPSEL.POEREQ0 bit is 1.
When the POECMPFR.C1FLAG flag becomes 1 while the POECR4.CMADDMT34ZE bit is 1 and the
POECMPSEL.POEREQ1 bit is 1.
When the POECMPFR.C2FLAG flag becomes 1 while the POECR4.CMADDMT34ZE bit is 1 and the
POECMPSEL.POEREQ2 bit is 1.
 Detection of oscillation stop
When the ICSR6.OSTSTF flag becomes 1 while the ICSR6.OSTSTE bit is 1.
(2) MTU4 pins (MTIOC4A, MTIOC4C)
When one of the following conditions is satisfied while the POECR2.MTU4ACZE bit is 1, the pins become high-
impedance.
 Operation for detection of the POE0# input level
When the ICSR1.POE0F flag becomes 1.
 Operation for comparison of the output levels on the MTIOC4A and MTIOC4C pins
When the OCSR1.OSF1 flag becomes 1 while the OCSR1.OCE1 bit is 1.
 SPOER setting
When the SPOER.MTUCH34HIZ bit is set to 1.
 Conditions added by POECR4
When the ICSR3.POE8F flag becomes 1 while the POECR4.IC3ADDMT34ZE bit and the ICSR3.POE8E bit are 1.
When the ICSR4.POE10F flag becomes 1 while the POECR4.IC4ADDMT34ZE bit and the ICSR4.POE10E bit are
1.
 Comparator output detection
When the POECMPFR.C0FLAG flag becomes 1 while the POECR4.CMADDMT34ZE bit is 1 and the
POECMPSEL.POEREQ0 bit is 1.
When the POECMPFR.C1FLAG flag becomes 1 while the POECR4.CMADDMT34ZE bit is 1 and the
POECMPSEL.POEREQ1 bit is 1.
When the POECMPFR.C2FLAG flag becomes 1 while the POECR4.CMADDMT34ZE bit is 1 and the
POECMPSEL.POEREQ2 bit is 1.
 Detection of oscillation stop
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
20. Port Output Enable 3 (POE3C)
Page 545 of 1041