Output-Level Compare Operation - Renesas RX100 Series User Manual

RX13T Group
(2) Low-Level Detection
Figure 20.5 shows an example of operation when a pin is placed in the high-impedance state in response to low-level
detection. When 16 continuous low levels are sampled with the sampling clock selected by the ICSR1 to ICSR4
registers, the low level is recognized and the outputs of the MTU complementary PWM output pins, and MTU0 pins are
in the high-impedance state. If even one high level is detected during this interval, the low level is not recognized.
The timing when the outputs of the MTU complementary PWM output pins, and MTU0 pins are in the high-impedance
state after the sampling clock is input is the same in both falling-edge detection and in low-level detection.
PCLK
Sampling clock
POE# pin input
MTIOC3B pin
When low level is
sampled at all points
When high level is
sampled at least once
Note 1. Other pins also become high-impedance at the same timing.
Figure 20.5 Operation when A Low-Level Detection is Selected
20.3.2

Output-Level Compare Operation

Figure 20.6 shows an example of the output-level compare operation for the combination of MTIOC3B and MTIOC3D.
The operation is the same for the other pin combinations.
PCLK
MTIOC3B pin
MTIOC3D pin
Note 1. When the active level of both MTIOC3B and MTIOC3D pins is set to low.
Figure 20.6 Output-Level Compare Operation
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
8/16/128 clock cycles
[1]
[2]
[1] [2]
20. Port Output Enable 3 (POE3C)
[3] [16]
[13]
Active-level overlapping detected
High-impedance
*1
High-impedance
Flag set (POE# pin received)
Flag not set
*1
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