Renesas RX100 Series User Manual page 776

RX13T Group
[10-bit address format: Slave reception]
S 1 2
SCL0
SDA0 1 1
BBSY
AASy
TRS
TDRE
RDRF
[10-bit address format: Slave transmission]
S 1 2
SCL0
SDA0
1 1
BBSY
AASy
TRS
TDRE
RDRF
Figure 24.25 AASy Flag Set Timing with 10-Bit Address Format Selected
[In the case of SARL0 : 7-bit address, SARL1 : 7-bit address, SAR2 : 10-bit address (1)]
S S 1 2
SCL0
SDA0
7-bit slave address (SARL0)
BBSY
AAS0
AAS1
AAS2
[In the case of SARL0 : 7-bit address, SARL1 : 7-bit address, SAR2 : 10-bit address (2)]
S 1 2
SCL0
SDA0 7-bit slave address (SARL1)
BBSY
AAS0
AAS1
AAS2
[In the case of SARL0 : 7-bit address, SARL1 : 7-bit address, SAR2 : 10-bit address (3)]
S 1 2
SCL0
SDA0 1 1
BBSY
AAS0
AAS1
AAS2
Figure 24.26 AASy Flag Set/Clear Timing with 7-Bit/10-Bit Address Formats Mixed
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
3 4 5 6 7 8
Upper 2 bits
1 1 0 W
3 4 5 6 7 8
Upper 2 bits
1 1 0 W
3 4 5 6 7 8 9
ACK
R/W
Address match
3 4 5 6 7 8 9
ACK
R/W
Address match
3 4 5 6 7 8 9
ACK
1 1 0 Upper 2 bits W Lower 8 bits
9 1 2 3 4 5
10-bit slave address (lower 8 bits)
ACK
9 1 to 8 9 Sr
Lower 8 bits
ACK ACK R
Address match
Receive data (lower addresses)
Read ICDRR register
(Dummy read [lower addresses])
1 to 8
9 Sr 1 2
ACK
DATA 7-bit slave address (SARL1)
1 to 8
9 Sr 1 2
ACK
DATA 1 1
1 to 8
9 Sr 1 2
ACK
7-bit slave address (SARL0)
Address match
2
24. I C-bus Interface (RIICa)
6 7 8 9 1 2 3
ACK
Address match
Receive data (lower addresses)
Read ICDRR register
(Dummy read [lower addresses])
1 2 3 4 5 6 7
Upper 2 bits
1 1 1 1 0
3 4 5 6 7 8 9
ACK
R/W
Address mismatch
Address match
3 4 5 6 7 8 9
ACK
1 1 0 Upper 2 bits W
Address mismatch
3 4 5 6 7 8 9
ACK
R/W
Address match
Address mismatch
Page 776 of 1041
4 5
Data
8 9
R ACK