Poe Setting Procedure; Interrupts - Renesas RX100 Series User Manual

RX13T Group
20.4

POE Setting Procedure

Figure 20.7 shows the procedure for setting the POE. It illustrates an example of high-impedance control in response to
comparison of the output levels on the MTU3 pins (MTIOC3B/MTIOC3D). In the figure, P71 is used as the MTIOC3B
pin and P74 is used as the MTIOC3D pin.
Start
Set the ALR1.OLSG0A and OLSG0B bits
to 0, and the ALR1.OLSEN bit to 1.
Set the POECR2.MTU3BDZE bit to 1.
Make the setting to operate MTU3.
End
Figure 20.7 Procedure for Setting the POE
20.5

Interrupts

The POE issues a request to generate an interrupt when the specified condition is satisfied during input-level detection or
output-level comparison. Table 20.4 shows the interrupt sources and their conditions.
Table 20.4 Interrupt Sources and Conditions
Name Interrupt Source
OEI1 Output enable interrupt 1
OEI3 Output enable interrupt 3
OEI4 Output enable interrupt 4
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
Set the MTU3 pins (P71 and P74) for the peripheral function by the
PMR register of the I/O port before making the following settings.
[1] Set the ALR1.OLSG0A and OLSG0B bits to 0 and the
ALR1.OLSEN bit to 1 to set MTIOC3B and MTIOC3D pins as
[1]
active low.
[2] Set the POECR2.MTU3BDZE bit to 1 to enable high-impedance
control on the MTIOC3B and MTIOC3D pins.
[2]
[3] Make the setting to operate MTU3 pin.
After the above settings, if MTIOC3B (P71) and MTIOC3D (P74)
[3]
pins are simultaneously at the low level, then the pins become high-
impedance and the OCSR1.OSF1 flag is set to 1.
For the method for releasing high-impedance, refer to section
20.3.7, Recover from High-Impedance State.
Interrupt Flag Condition
POE0F When the ICSR1.POE0F flag becomes 1 while the
OSF1 ICSR1.PIE1 bit is 1 or when the OCSR1.OSF1 flag becomes 1
while the OCSR1.OIE1 bit is 1
POE8F When the ICSR3.POE8F flag becomes 1 while the
ICSR3.PIE3 bit is 1
POE10F When the ICSR4.POE10F flag is set to 1 while the
ICSR4.PIE4 bit is 1
20. Port Output Enable 3 (POE3C)
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