Flash P/E Mode Entry Register (Fentryr) - Renesas RX100 Series User Manual

RX13T Group
31.4.2

Flash P/E Mode Entry Register (FENTRYR)

Address(es): FLASH.FENTRYR 007F FFB2h
b15 b14
0 0
Value after reset:
Bit Symbol Bit Name
b0 FENTRY0 ROM P/E Mode Entry 0
b6 to b1 — Reserved
b7 FENTRYD E2 DataFlash P/E Mode
Entry
b15 to b8 FEKEY[7:0] Key Code
To rewrite the ROM or E2 DataFlash, the FENTRYD or FENTRY0 bit must be set to 1 to place the ROM or E2
DataFlash in P/E mode.
When returning to read mode, set the FENTRYR register and confirm that its value has been rewritten before reading the
ROM or E2 DataFlash.
Refer to section 31.7.1, Sequencer Modes for details on P/E mode and read mode.
FENTRY0 Bit (ROM P/E Mode Entry 0)
This bit is used to place the ROM in P/E mode.
[Setting condition]
 AA01h is written to the FENTRYR register when the FENTRYR register is 0000h.
Note: When entering ROM P/E mode, the instruction fetch address must be transferred to an area other than the ROM
so that instruction fetching is not executed to the ROM. Copy necessary instruction code to the internal RAM and
jump to the RAM. Note that E2 DataFlash can be rewritten by a program in the ROM.
[Clearing condition]
 AA00h is written to the FENTRYR register.
FENTRYD Bit (E2 DataFlash P/E Mode Entry)
This bit is used to place the E2 DataFlash in P/E mode.
[Setting condition]
 AA80h is written to the FENTRYR register when the FENTRYR register is 0000h.
[Clearing condition]
 AA00h is written to the FENTRYR register.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b13 b12 b11 b10
FEKEY[7:0]
0 0 0 0
Description
0: ROM is in read mode.
1: ROM can be placed in P/E mode.
These bits are read as 0. The write value should be 0.
0: E2 DataFlash is in read mode.
1: E2 DataFlash can be placed in P/E mode.
The FEKEY[7:0] bits are used to control rewriting of the FENTRYR
register.
When rewriting the value of the lower 8 bits, set the FEKEY[7:0] bits to
AAh at the same time (write this register in 16 bits).
The FEKEY[7:0] bits are read as 00h.
b9 b8 b7 b6
FENTR
—
YD
0 0 0 0
31. Flash Memory (FLASH)
b5 b4 b3 b2
— — — —
0 0 0 0
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b1 b0
FENTR
—
Y0
0 0
R/W
R/W
R/W
R/W
R/W