Renesas RX100 Series User Manual page 328

32-bit mcu
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RX13T Group
Table 19.4
CCLR[2:0] (MTU0, MTU3, MTU4)
Bit 7
Bit 6
Channel
CCLR[2]
CCLR[1]
MTU0
0
0
MTU3
0
0
MTU4
0
1
0
1
1
0
1
0
1
1
1
1
Note 1. Synchronous operation is selected by setting the TSYRA.SYNC bit to 1
Note 2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the buffer register setting has priority and
compare match/input capture does not occur.
Table 19.5
CCLR[2:0] (MTU1 and MTU2)
Bit 7
2
Channel
Reserved*
MTU1
0
MTU2
0
0
0
Note 1. Synchronous operation is selected by setting the TSYRA.SYNC bit to 1.
Note 2. Bit 7 is reserved in MTU1 and MTU2. It is read as 0. The write value is ignored.
 MTU5.TCRU, MTU5.TCRV, MTU5.TCRW
Address(es): MTU5.TCRU 0009 5484h, MTU5.TCRV 0009 5494h, MTU5.TCRW 0009 54A4h
b7
b6
Value after reset:
0
0
Bit
Symbol
b1, b0
TPSC[1:0]
b7 to b2
TPSC[1:0] Bits (Time Prescaler Select)
These bits select the TCNT count clock source. Refer to Table 19.10 for details.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
Bit 5
CCLR[0]
Description
0
TCNT clearing disabled
1
TCNT cleared by TGRA compare match/input capture
0
TCNT cleared by TGRB compare match/input capture
1
TCNT cleared by counter clearing in another channel performing synchronous clearing/
synchronous operation*
0
TCNT clearing disabled
1
TCNT cleared by TGRC compare match/input capture*
0
TCNT cleared by TGRD compare match/input capture*
1
TCNT cleared by counter clearing in another channel performing synchronous clearing/
synchronous operation*
Bit 6
Bit 5
CCLR[1]
CCLR[0]
Description
0
0
TCNT clearing disabled
0
1
TCNT cleared by TGRA compare match/input capture
1
0
TCNT cleared by TGRB compare match/input capture
1
1
TCNT cleared by counter clearing in another channel performing synchronous
clearing/synchronous operation*
b5
b4
b3
b2
0
0
0
0
Bit Name
Time Prescaler Select
Reserved
19. Multi-Function Timer Pulse Unit 3 (MTU3c)
1
1
1
b1
b0
TPSC[1:0]
0
0
Description
Refer to Table 19.10.
These bits are read as 0. The write value should be 0.
2
2
R/W
R/W
R/W
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