Timer Mode Register 3 (Tmdr3) - Renesas RX100 Series User Manual

RX13T Group
19.2.5

Timer Mode Register 3 (TMDR3)

Address(es): MTU1.TMDR3 0009 5391h
b7 b6
— —
Value after reset: 0 0
Bit Symbol Bit Name
b0 LWA MTU1/MTU2 Combination
Longword Access Control
b1 PHCKSEL External Input Phase Clock
Select
b7 to b2 — Reserved
The TMDR3 register controls longword access to a 32-bit register or counter in a combination of MTU1 and MTU2.
There is only one TMDR3 register in MTU1. The counter (TCNTLW), general register A (TGRALW), and general
register B (TGRBLW) of MTU1 and MTU2 are accessed in the combinations listed in Table 19.12 .
LWA Bit (MTU1/MTU2 Combination Longword Access Control)
This bit selects a 32-bit access in a combination of MTU1 and MTU2.
When LWA is set to 0, the MTU1 and MTU2 independently operate as a 16-bit timer. therefore registers TCNTLW,
TGRALW, and TGRBLW cannot be accessed.
When LWA is set to 1, MTU1 and MTU2 operate as a 32-bit cascaded timer and the timer is controlled by registers
MTU1.TCR, MTU1.TCR2, MTU1.TIOR, and MTU1.TMDR1. The settings of registers MTU2.TCR, MTU2.TCR2,
MTU2.TIOR, and MTU2.TMDR1 are disabled and the 16-bit registers (TCNT, TGRA, and TGRB) in MTU1 and MTU2
cannot be accessed. Furthermore, MTU2 input capture and compare match are also disabled.
The cascaded connection of MTU1 and MTU2 with the LWA bit set to 1 can only be used in phase counting mode, but
not in normal mode, PWM1 mode, or PWM2 mode. Select phase counting mode when setting the LWA bit to 1.
Initialize the registers TCNT, TGRA, and TGRB in MTU1 and MTU2 in advance before setting the LWA bit to 1.
PHCKSEL Bit (External Input Phase Clock Select)
When the MTU1 and MTU2 registers are combined for 32-bit phase counting mode or MTU2 phase counting mode, this
bit selects either the A- or B-phase signal from the external clock. Refer to Table 19.50, Clock Input Pins in Phase
Counting Mode for details.
Table 19.12 Setting and Combination of the TMDR3 Register
Register
1
Counter in MTU1*
Counter in MTU2
General register A in MTU1
General register A in MTU2
General register B in MTU1
General register B in MTU2
Note 1. When the LWA bit is set to 1, setting the count clock for MTU1 as MTU2.TCNT overflow/underflow is not required.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b5 b4 b3 b2
PHCKS
— — — —
0 0 0 0
Description
0: 16-bit access is enabled.
1: 32-bit access is enabled.
0: MTCLKA and MTCLKB are selected for the external phase clock.
1: MTCLKC and MTCLKD are selected for the external phase clock.
These bits are read as 0. The write value should be 0.
TMDR3.LWA = 0
Symbol
MTU1.TCNT
MTU2.TCNT
MTU1.TGRA
MTU2.TGRA
MTU1.TGRB
MTU2.TGRB
19. Multi-Function Timer Pulse Unit 3 (MTU3c)
b1 b0
LWA
EL
1 0
TMDR3.LWA = 1
Access mode Symbol
Word MTU1.TCNTLW
Word
Word MTU1.TGRALW
Word
Word MTU1.TGRBLW
Word
R/W
R/W
R/W
R/W
Access mode
Longword
Longword
Longword
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