Renesas RX100 Series User Manual page 454

RX13T Group
(c) Buffer Transfer Control Linked with Interrupt Skipping
In complementary PWM mode, whether to transfer data from a buffer register to a temporary register and whether to link
the transfer with interrupt skipping can be specified with the BTE[1:0] bits in the TBTERA register.
Figure 19.80 shows an example of operation when buffer transfer is disabled (BTE[1:0] = 01b). While this setting is
valid, data is not transferred from the buffer register to the temporary register.
Figure 19.81 shows an example of operation when buffer transfer is linked with interrupt skipping (BTE[1:0] = 10b).
While this setting is valid, data is not transferred from the buffer register outside the buffer transfer-enabled period.
Note that the buffer transfer-enabled period differs depending on whether only the T3AEN bit in the TITCR1A register is
set to 1, only the T4VEN bit in the TITCR1A register is set to 1, or both the T3AEN and T4VEN bits are set to 1. Figure
19.82 shows the relationship between the T3AEN and T4VEN bit settings in TITCR1A and buffer transfer-enabled
period.
Note: This function must be used in combination with interrupt skipping function 1.
When interrupt skipping is disabled (the T3AEN and T4VEN bits in the timer interrupt skipping set register 1
(TITCR1A) are set to 0 or the skipping count set bits (T3ACOR and T4VCOR) in TITCR1A are set to 0), make
sure that buffer transfer is not linked with interrupt skipping (set the BTE1 bit in TBTERA to 0).
If buffer transfer is linked with interrupt skipping while interrupt skipping is disabled, buffer transfer is never
performed.
MTU3.TCNT
MTU4.TCNT
TCNTSA
TBTERA.BTE0 bit
TBTERA.BTE1 bit
Buffer register
Temporary register
Compare register
(1) No data is transferred from the buffer register to the temporary register in the buffer transfer-disabled
period (bits BTE[1:0] in TBTERA are set to 01b).
(2) Data is transferred from the temporary register to the compare register even in the buffer transfer-
disabled period.
(3) After buffer transfer is enabled, data is transferred from the buffer register to the temporary register.
Note 1. When buffer transfer at the crest is selected.
Figure 19.80 Example of Operation When Buffer Transfer is Disabled (BTE[1:0] = 01b)
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
MTU3.
TCNT
MTU4.
TCNT
Data 1
(1)
*1
Data
(2)
*1
Data
Buffer transfer is suppressed
19. Multi-Function Timer Pulse Unit 3 (MTU3c)
Data 2
(3)
Data 2
Data 2
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