Renesas RX100 Series User Manual page 536

RX13T Group
OLSG2A Bit (MTIOC4B Pin Active Level Setting)
This bit sets the active level of the MTIOC4B output. Specifically, setting the OLSG2A bit to 0 sets the low level and to
1 sets the high level as the active level for detection of simultaneous conduction.
OLSG2B Bit (MTIOC4D Pin Active Level Setting)
This bit sets the active level of the MTIOC4D output. Specifically, setting the OLSG2B bit to 0 sets the low level and to
1 sets the high level as the active level for detection of simultaneous conduction.
OLSEN Bit (Active Level Setting Enable)
This bit enables or disables of the active-level settings in the OLSGnm bits (n = 0 to 2; m = A, B). Clearing the OLSEN
bit to 0 disables the OLSGnm bits, in which case the active levels of the MTU output are determined by the
MTU.TOCR1A and MTU.TOCR2A registers. Setting the OLSEN bit to 1 enables the OLSGnm bits, in which case the
active levels of the MTU output are as selected by the OLSGnm bits in this register.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
20. Port Output Enable 3 (POE3C)
Page 536 of 1041