Usage Notes; Module Stop Function Setting; Count Clock Restrictions; Note On Period Setting - Renesas RX100 Series User Manual

RX13T Group
19.6

Usage Notes

19.6.1

Module Stop Function Setting

MTU operation can be disabled or enabled using the module stop control register. MTU operation is stopped with the
initial setting. Register access is enabled by releasing the module clock stop state. For details, refer to section 11, Low
Power Consumption .
19.6.2

Count Clock Restrictions

The count clock source pulse width must be at least three PCLKB cycles for single-edge detection, and at least five
PCLKB cycles for both-edge detection. The MTU will not operate properly at narrower pulse widths.
In phase counting mode, the phase difference and overlap between the two input clocks must be at least three PCLKB
cycles, and the pulse width must be at least five PCLKB cycles. Figure 19.122 shows the input clock conditions in
phase counting mode.
MTCLKA (MTCLKC)
MTCLKB (MTCLKD)
Figure 19.122 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode
19.6.3

Note on Period Setting

When counter clearing on compare match is set, TCNT is cleared in the final state in which it matches the TGR value
(the point at which TCNT updates the matched count value). Consequently, the actual counter frequency is given by the
following formula:
 MTU0 to MTU4
CNTCLK
f = ------------------------ -
N 1
+
 MTU5
CNTCLK
f
= ------------------------ -
N
f: Counter frequency
CNTCLK: The count clock frequency set by TCR.TPSC[2:0] and TCR2.TPSC2[2:0]
N: TGR setting
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
Phase
Phase
differ-
differ-
Overlap Overlap
ence
ence
Pulse width Pulse width
Note: Phase difference and overlap: 3 PCLKB cycles or more
Note: Pulse width: 5 PCLKB cycles or more
19. Multi-Function Timer Pulse Unit 3 (MTU3c)
Pulse width Pulse width
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