Timer Counter (Tcnt); Timer Longword Counter (Tcntlw) - Renesas RX100 Series User Manual

RX13T Group
19.2.12

Timer Counter (TCNT)

Address(es): MTU0.TCNT 0009 5306h, MTU1.TCNT 0009 5386h, MTU2.TCNT 0009 5406h, MTU3.TCNT 0009 5210h,
MTU4.TCNT 0009 5212h, MTU5.TCNTU 0009 5480h, MTU5.TCNTV 0009 5490h, MTU5.TCNTW 0009 54A0h
b15 b14
0 0
Value after reset:
Note: TCNT must not be accessed in 8 bits; it should be accessed in 16 bits.
TCNT is a 16-bit readable/writable counter. The MTU has a total of eight TCNT counters, one each for MTU0 to MTU4
and three (MTU5.TCNTU, TCNTV, and TCNTW) for MTU5. The TCNT counters in MTU0 to MTU4 are initialized to
0000h by a reset. MTU5.TCNTU, MTU5.TCNTV, and MTU5.TCNTW are initialized to 0000h by a reset.
In MTU0 to MTU4, the TCNT counters must not be accessed in 8-bit units; they should be accessed in 16-bit units.
The MTU1.TCNT and MTU2.TCNT counters are read as 0000h when TMDR3.LWA is 1. Refer to section 19.2.5,
Timer Mode Register 3 (TMDR3) for details.
19.2.13

Timer Longword Counter (TCNTLW)

Address(es): MTU1.TCNTLW 0009 53A0h
b31 b30
0 0
Value after reset:
b15 b14
0 0
Value after reset:
Note: TCNTLW must not be accessed in 8 or 16 bits; it should be accessed in 32 bits.
The TCNTLW counter is a 32-bit readable/writable counter. Only one counter of this type is provided, and is formed by
combining MTU1.TCNT and MTU2.TCNT. Such operation is only effective when TMDR3.LWA is 1. The TCNTLW
counter is initialized to 0000 0000h by a reset. This counter is read as 0000 0000h when TMDR3.LWA is 0. Refer to
section 19.2.5, Timer Mode Register 3 (TMDR3) for details. This register can only be used in 32-bit phase counting
mode.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b13 b12 b11 b10
0 0 0 0
b29 b28 b27 b26
0 0 0 0
b13 b12 b11 b10
0 0 0 0
19. Multi-Function Timer Pulse Unit 3 (MTU3c)
b9 b8 b7 b6
0 0 0 0
b25 b24 b23 b22
0 0 0 0
b9 b8 b7 b6
0 0 0 0
b5 b4 b3 b2
0 0 0 0
b21 b20 b19 b18
0 0 0 0
b5 b4 b3 b2
0 0 0 0
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b1 b0
0 0
b17 b16
0 0
b1 b0
0 0