I 2 C-Bus Bit Rate High-Level Register (Icbrh) - Renesas RX100 Series User Manual

RX13T Group
2
24.2.14 I C-bus Bit Rate High-Level Register (ICBRH)
Address(es): RIIC0.ICBRH 0008 8311h
b7 b6
— —
1 1
Value after reset:
Bit Symbol Bit Name
b4 to b0 BRH[4:0] Bit Rate High-Level Period
b7 to b5 — Reserved
ICBRH is a 5-bit register to set the high-level period of SCL clock. ICBRH is valid in master mode. If the RIIC is used
only in slave mode, this register need not to set the high-level period.
ICBRH counts the high-level period with the internal reference clock (IICφ) specified by the ICMR1.CKS[2:0] bits.
If the digital noise filter is enabled (the ICFER.NFE bit is 1), set the ICBRH register to a value at least one greater than
the number of stages in the noise filter. Regarding the number of stages in the noise filter, see the description of the
ICMR3.NF[1:0] bits.
2
The I C transfer rate and the SCL clock duty are calculated using the following expression.
Transfer rate = 1 / {[(ICBRH + 1) + (ICBRL + 1)] / IICφ *
Duty cycle = {SCL0 line rising time [tr] *
Note 1. IICφ = PCLK × Division ratio
Note 2. The SCL0 line rising time [tr] and SCL0 line falling time [tf] depend on the total bus line capacitance [Cb] and the
pull-up resistor [Rp]. For details, see the I
Table 24.5 lists examples of ICBRH/ICBRL settings.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b5 b4 b3 b2
— BRH[4:0]
1 1 1 1
Description
High-level period of SCL clock
These bits are read as 1. The write value should be 1.
2
+ (ICBRH + 1) / IICφ} / {SCL0 line falling time [tf] *
2
C-bus specification from NXP Semiconductors.
b1 b0
1 1
1
+ SCL0 line rising time [tr] + SCL0 line falling time [tf]}
2
24. I C-bus Interface (RIICa)
R/W
R/W
R/W
2
+ (ICBRL + 1) / IICφ}
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