Timer Input Capture Control Register (Ticcr) - Renesas RX100 Series User Manual

32-bit mcu
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19.2.11

Timer Input Capture Control Register (TICCR)

Address(es): MTU1.TICCR 0009 5390h
b7
b6
Value after reset:
0
0
Bit
Symbol
Bit Name
b0
I1AE
Input Capture Enable
b1
I1BE
Input Capture Enable
b2
I2AE
Input Capture Enable
b3
I2BE
Input Capture Enable
b7 to b4
Reserved
TICCR specifies input capture conditions when MTU1.TCNT and MTU2.TCNT are cascaded. The MTU has one
TICCR for MTU1.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b5
b4
b3
b2
I2BE
I2AE
0
0
0
0
19. Multi-Function Timer Pulse Unit 3 (MTU3c)
b1
b0
I1BE
I1AE
0
0
Description
0: Does not include the MTIOC1A pin in the MTU2.TGRA input
capture conditions
1: Includes the MTIOC1A pin in the MTU2.TGRA input capture
conditions
0: Does not include the MTIOC1B pin in the MTU2.TGRB input
capture conditions
1: Includes the MTIOC1B pin in the MTU2.TGRB input capture
conditions
0: Does not include the MTIOC2A pin in the MTU1.TGRA input
capture conditions
1: Includes the MTIOC2A pin in the MTU1.TGRA input capture
conditions
0: Does not include the MTIOC2B pin in the MTU1.TGRB input
capture conditions
1: Includes the MTIOC2B pin in the MTU1.TGRB input capture
conditions
These bits are read as 0. The write value should be 0.
R/W
R/W
R/W
R/W
R/W
R/W
Page 354 of 1041

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