Fast Interrupt Set Register (Fir) - Renesas RX100 Series User Manual

RX13T Group
14.2.4

Fast Interrupt Set Register (FIR)

Address(es): ICU.FIR 0008 72F0h
b15 b14
FIEN —
Value after reset: 0 0
Bit Symbol Bit Name
b7 to b0 FVCT[7:0] Fast Interrupt Vector Number
b14 to b8 — Reserved
b15 FIEN Fast Interrupt Enable
The fast interrupt function based on the FIR register setting is applicable only to interrupts to the CPU. It will not affect
any transfer request to the DTC.
Before writing to this register, be sure to disable interrupt requests (IERm.IENj bit = 0 (m = 02h to 1Fh, j = 0 to 7)).
FVCT[7:0] Bits (Fast Interrupt Vector Number)
The FVCT[7:0] bits specify the vector number of an interrupt source that uses the fast interrupt function.
FIEN Bit (Fast Interrupt Enable)
This bit enables the fast interrupt.
Setting this bit to 1 makes the interrupt request of the vector number specified by the FVCT[7:0] bits a fast interrupt.
When an interrupt request of the vector number specified by the FVCT[7:0] bits is generated and the interrupt request
destination is the CPU while the FIEN bit is 1, the interrupt request is output to the CPU as a fast interrupt regardless of
the setting of the IPRn register (n = interrupt vector number). When using the fast interrupt for returning from the
software standby mode, see section 14.6.2, Return from Software Standby Mode .
If the setting of the IERm.IENj bit has disabled interrupt requests from the interrupt source with the vector number in this
register, fast interrupt requests are not output to the CPU.
For settable vector numbers, see Table 14.3, Interrupt Vector Table .
Do not write any reserved vector numbers to the FVCT[7:0] bits.
For details on the fast interrupt, see section 13, Exception Handling , and section 14.4.6, Fast Interrupt .
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b13 b12 b11 b10
— — — —
0 0 0 0
Description
Specify the vector number of an interrupt source to be a fast
interrupt.
These bits are read as 0. The write value should be 0.
0: Fast interrupt is disabled
1: Fast interrupt is enabled
b9 b8 b7 b6
— —
0 0 0 0
14. Interrupt Controller (ICUb)
b5 b4 b3 b2
FVCT[7:0]
0 0 0 0
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b1 b0
0 0
R/W
R/W
R/W
R/W