Bus Error Status Register 1 (Bersr1); Bus Error Status Register 2 (Bersr2) - Renesas RX100 Series User Manual

RX13T Group
15.3.3

Bus Error Status Register 1 (BERSR1)

Address(es): 0008 1308h
b7 b6
—
0 0
Value after reset:
Bit Symbol
b0 IA
b1 TO
b3, b2 —
b6 to b4 MST[2:0]
b7 —
MST[2:0] Bits (Bus Master Code)
These bits indicate the bus master that accessed a bus when a bus error occurred.
15.3.4

Bus Error Status Register 2 (BERSR2)

Address(es): 0008 130Ah
b15 b14
0 0
Value after reset:
Bit Symbol
b2 to b0 —
b15 to b3 ADDR[12:0]
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b5 b4 b3 b2
MST[2:0] — —
0 0 0 0
Bit Name
Illegal Address Access
Timeout
Reserved
Bus Master Code
Reserved
b13 b12 b11 b10
ADDR[12:0]
0 0 0 0
Bit Name Description
Reserved These bits are read as 0. Writing to these bits has no effect.
Bus Error The upper 13 bits of an address that was accessed when a bus error
Occurrence Address occurred (in units of 512 Kbytes).
b1 b0
TO IA
0 0
Description
0: Illegal address access not made
1: Illegal address access made
0: Timeout not generated
1: Timeout generated
These bits are read as 0. Writing to these bits has no effect.
b6 b4
0 0 0: CPU
0 0 1: Reserved
0 1 0: Reserved
0 1 1: DTC
1 0 0: Reserved
1 0 1: Reserved
1 1 0: Reserved
1 1 1: Reserved
This bit is read as 0. Writing to this bit has no effect.
b9 b8 b7 b6
0 0 0 0
b5 b4 b3 b2
—
0 0 0 0
Page 239 of 1041
15. Buses
R/W
R
R
R
R
R
b1 b0
— —
0 0
R/W
R
R