Extended Serial Module Enable Register (Esmer) - Renesas RX100 Series User Manual

RX13T Group
MFF Flag (Mode Fault Flag)
This bit indicates mode fault errors.
In a multi-master configuration, determine the mode fault error occurrence by reading the MFF flag.
[Setting condition]
 Input on the SSn# pin being at the low level during master operation in simple SPI mode (SSE bit = 1 and MSS bit
= 0)
[Clearing condition]
 Writing 0 to the bit after it was read as 1
CKPOL Bit (Clock Polarity Select)
This bit selects the polarity of the clock signal output through the SCKn pin. Refer to Figure 23.57 for details.
Set the bit to 0 in other than simple SPI mode and clock synchronous mode.
CKPH Bit (Clock Phase Select)
This bit selects the phase of the clock signal output through the SCKn pin. Refer to Figure 23.57 for details.
Set the bit to 0 in other than simple SPI mode and clock synchronous mode.
23.2.20

Extended Serial Module Enable Register (ESMER)

Address(es): SCI12.ESMER 0008 B320h
b7 b6
— —
0 0
Value after reset:
Bit Symbol Bit Name
b0 ESME Extended Serial Mode
Enable
b7 to b1 — Reserved
ESME Bit (Extended Serial Mode Enable)
When the ESME bit is 1, the facilities of the extended serial mode control section are enabled.
When the ESME bit is 0, the extended serial mode control section is initialized.
Table 23.26 Settings of the ESME Bit and Timer Operation Mode
ESME Bit Timer Mode
0 Available*
1 Available
Note 1. Operation is only possible with PCLK selected.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b5 b4 b3 b2
— — — —
0 0 0 0
Description
0: The extended serial mode is disabled.
1: The extended serial mode is enabled.
These bits are read as 0. The write value should be 0.
Break Field Low Width Determination Mode
1
Not available
Available
23. Serial Communications Interface (SCIg, SCIh)
b1 b0
— ESME
0 0
Break Field Low Width Output Mode
Not available
Available
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R/W
R/W
R/W