Noise Filter Control Register 5 (Nfcr5) - Renesas RX100 Series User Manual

RX13T Group
NFCS[1:0] Bits (Noise Filter Clock Select)
These bits set the sampling interval for the noise filters. After setting the NFCS[1:0] bits, wait for two cycles of the
selected sampling interval to set the input capture function.
19.2.33

Noise Filter Control Register 5 (NFCR5)

Address(es): MTU5.NFCR5 0009 5295h
b7 b6
— —
0 0
Value after reset:
Bit Symbol Bit Name
b0 NFUEN Noise Filter U Enable
b1 NFVEN Noise Filter V Enable
b2 NFWEN Noise Filter W Enable
b3 — Reserved
b5, b4 NFCS[1:0] Noise Filter Clock Select
b7, b6 — Reserved
NFUEN Bit (Noise Filter U Enable)
This bit disables or enables the noise filter for input from the MTIC5U pin. Since unexpected edges may be internally
generated when the value of this bit is changed, select the output compare function for the relevant pin in the timer I/O
control register.
NFVEN Bit (Noise Filter V Enable)
This bit disables or enables the noise filter for input from the MTIC5V pin. Since unexpected edges may be internally
generated when the value of this bit is changed, select the output compare function for the relevant pin in the timer I/O
control register.
NFWEN Bit (Noise Filter W Enable)
This bit disables or enables the noise filter for input from the MTIC5W pin. Since unexpected edges may be internally
generated when the value of this bit is changed, select the output compare function for the relevant pin in the timer I/O
control register.
NFCS[1:0] Bits (Noise Filter Clock Select)
These bits set the sampling interval for the noise filters. When setting the NFCS[1:0] bits, wait for two cycles of the
selected sampling interval before setting the input-capture function.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b5 b4 b3 b2
NFWE
NFCS[1:0] — NFVEN NFUEN
N
0 0 0 0
19. Multi-Function Timer Pulse Unit 3 (MTU3c)
b1 b0
0 0
Description
0: The noise filter for the MTIC5U pin is disabled.
1: The noise filter for the MTIC5U pin is enabled.
0: The noise filter for the MTIC5V pin is disabled.
1: The noise filter for the MTIC5V pin is enabled.
0: The noise filter for the MTIC5W pin is disabled.
1: The noise filter for the MTIC5W pin is enabled.
This bit is read as 0. The write value should be 0.
b5 b4
0 0: PCLKB/1
0 1: PCLKB/8
1 0: PCLKB/32
1 1: Clock source for counting
These bits are read as 0. The write value should be 0.
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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