Interrupt Operation; Detecting Interrupts; Operation Of Status Flags For Edge-Detected Interrupts - Renesas RX100 Series User Manual

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Interrupt Operation

The interrupt controller performs the following processing.

 Detecting interrupts

 Enabling and disabling interrupts

 Selecting interrupt request destinations (CPU interrupt or DTC trigger)

 Determining priority

Interrupt requests are detected in either of two ways: the detection of edges of the interrupt signal or the detection of a

level of the interrupt signal.

Edge detection or level detection is selected for the IRQi pins (i = 0 to 5) as external interrupt requests by the setting of

the IRQMD[1:0] bits in IRQCRi.

For interrupts from peripheral modules, either edge detection or level detection is determined per interrupt source.

For the correspondence between interrupt sources and methods of detection, see Table 14.3, Interrupt Vector Table .

Figure 14.2 shows the operation of the IR flag in IRn (n = interrupt vector number) in the case of edge detection of an

interrupt from a peripheral module or on an external pin.

The IR flag in IRn is set to 1 immediately after the transition of the interrupt signal due to generation of the interrupt. If

the CPU is the request destination for the interrupt, the IR flag is automatically cleared to 0 on acceptance of the

interrupt. If the DTC is the request destination for the interrupt, the IRn.IR flag operation differs according to the DTC

transfer settings and transfer count. For details, see Table 14.4, Operation When Starting the DTC .

Peripheral module clock

Note 1. One of the following requests is issued: CPU interrupt request, DTC transfer request. For details of the setting, see

section 14.4.3, Selecting Interrupt Request Destinations.

Note 2. When the CPU interrupt request is specified, this flag is set to 0 on acceptance of a CPU interrupt. For the timing of 0

setting at the DTC transfer request, see Table 14.4, Operation When Starting the DTC.

IRn.IR Flag Operation for Edge Detection Interrupts

R01UH0822EJ0100 Rev.1.00

Jul 31, 2019

Interrupt signal

System clock

CPU interrupt request

DTC transfer request

14. Interrupt Controller (ICUb)

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