Independent Watchdog Timer (Iwdta); Overview - Renesas RX100 Series User Manual

RX13T Group
22.

Independent Watchdog Timer (IWDTa)

In this section, "PCLK" is used to refer to PCLKB.
22.1

Overview

The independent watchdog timer (IWDT) can be used to detect programs being out of control.
The user can detect when a program runs out of control if an underflow occurs, by creating a program that refreshes the
IWDT counter before it underflows.
The functions of the IWDT are different from those of the WDT in the following respects.
 The divided IWDT-dedicated clock (IWDTCLK) is used as the count source (not affected by the PCLK).
 When making a transition to sleep mode, software standby mode, or deep sleep mode, the IWDTCSTPR.SLCSTP
bit or the OFS0.IWDTSLCSTP bit can be used to select whether to stop the counter or not.
Table 22.1 lists the specifications of the IWDT and Figure 22.1 shows a block diagram of the IWDT.
Table 22.1 IWDT Specifications
Item
1
Count source*
Clock divide ratio
Counter operation
Conditions for starting the
counter
Conditions for stopping the
counter
Window function
Reset output sources
Non-maskable interrupt
sources
Reading the counter value
Output signal (internal signal)
Auto-start mode
(controlled by option function
select register 0 (OFS0))
Register start mode
(controlled by the IWDT
registers)
Note 1. Satisfy the frequency of the peripheral module clock (PCLK)  4 × (the frequency of the count source after divide).
Note 2. When the OFS0.IWDTSLCSTP bit is 1 in auto-start mode, and when the IWDTCSTPR.SLCSTP bit is 1 in register start mode.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
Description
IWDT-dedicated clock (IWDTCLK)
Divide by 1, 16, 32, 64, 128, or 256
Counting down using a 14-bit down-counter
 Auto-start mode: Counting automatically starts after a reset is released
 Register start mode: Counting is started by refresh operation (writing 00h and then FFh to the
IWDTRR register).
 Reset (the down-counter and other registers return to their initial values)
 In low power consumption states (depends on the register setting*
 A counter underflows or a refresh error occurs (only in register start mode)
Window start and end positions can be specified (refresh-permitted and refresh-prohibited periods)
 Down-counter underflows
 Refreshing outside the refresh-permitted period (refresh error)
 Down-counter underflows
 Refreshing outside the refresh-permitted period (refresh error)
The down-counter value can be read by the IWDTSR register.
 Reset output
 Interrupt request output
 Sleep mode count stop control output
 Selecting the clock frequency divide ratio after a reset (OFS0.IWDTCKS[3:0] bits)
 Selecting the timeout period of the independent watchdog timer (OFS0.IWDTTOPS[1:0] bits)
 Selecting the window start position in the independent watchdog timer (OFS0.IWDTRPSS[1:0] bits)
 Selecting the window end position in the independent watchdog timer (OFS0.IWDTRPES[1:0] bits)
 Selecting the reset output or interrupt request output (OFS0.IWDTRSTIRQS bit)
 Selecting the down-count stop function at transition to sleep mode, software standby mode, or
deep sleep mode (OFS0.IWDTSLCSTP bit)
 Selecting the clock frequency divide ratio after refreshing (IWDTCR.CKS[3:0] bits)
 Selecting the timeout period of the independent watchdog timer (IWDTCR.TOPS[1:0] bits)
 Selecting the window start position in the independent watchdog timer (IWDTCR.RPSS[1:0] bits)
 Selecting the window end position in the independent watchdog timer (IWDTCR.RPES[1:0] bits)
 Selecting the reset output or interrupt request output (IWDTRCR.RSTIRQS bit)
 Selecting the down-count stop function at transition to sleep mode, software standby mode, or
deep sleep mode (IWDTCSTPR.SLCSTP bit)
22. Independent Watchdog Timer (IWDTa)
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