Interrupt Control Register (Icr) - Renesas RX100 Series User Manual

RX13T Group
23.2.26

Interrupt Control Register (ICR)

Address(es): SCI12.ICR 0008 B326h
b7 b6
— —
Value after reset: 0 0
Bit Symbol Bit Name
b0 BFDIE Break Field Low Width Detected
Interrupt Enable
b1 CF0MIE Control Field 0 Match Detected
Interrupt Enable
b2 CF1MIE Control Field 1 Match Detected
Interrupt Enable
b3 PIBDIE Priority Interrupt Bit Detected Interrupt
Enable
b4 BCDIE Bus Collision Detected Interrupt Enable
b5 AEDIE Valid Edge Detected Interrupt Enable
b7, b6 — Reserved
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b5 b4 b3 b2
AEDIE BCDIE PIBDIE CF1MI
E
0 0 0 0
23. Serial Communications Interface (SCIg, SCIh)
b1 b0
CF0MI
BFDIE
E
0 0
Description
0: Interrupts on detection of the low width for a Break Field
are disabled.
1: Interrupts on detection of the low width for a Break Field
are enabled.
0: Interrupts on detection of a match with Control Field 0 are
disabled.
1: Interrupts on detection of a match with Control Field 0 are
enabled.
0: Interrupts on detection of a match with Control Field 1 are
disabled.
1: Interrupts on detection of a match with Control Field 1 are
enabled.
0: Interrupts on detection of the priority interrupt bit are
disabled.
1: Interrupts on detection of the priority interrupt bit are
enabled.
0: Interrupts on detection of a bus collision are disabled.
1: Interrupts on detection of a bus collision are enabled.
0: Interrupts on detection of a valid edge are disabled.
1: Interrupts on detection of a valid edge are enabled.
These bits are read as 0. The write value should be 0.
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Page 629 of 1041