Digital Noise Filter Circuit - Renesas RX100 Series User Manual

RX13T Group
24.6

Digital Noise Filter Circuit

The states of the SCL0 and SDA0 pins are conveyed to the internal circuitry through analog noise-filter and digital noise-
filter circuits. Figure 24.23 is a block diagram of the digital noise-filter circuit.
The on-chip digital noise-filter circuit of the RIIC consists of four flip-flop circuit stages connected in series and a match-
detection circuit.
The number of effective stages in the digital noise filter is selected by the ICMR3.NF[1:0] bits. The selected number of
effective stages determines the noise-filtering capability as a period from one to four IICφ cycles.
The input signal to the SCL0 pin (or SDA0 pin) is sampled on falling edges of the IICφ signal. When the input signal
level matches the output level of the number of effective flip-flop circuit stages as selected by the ICMR3.NF[1:0] bits,
the signal level is conveyed to the subsequent stage. If the signal levels do not match, the previous value is retained.
If the ratio between the frequency of the internal operating clock (PCLK) and the transfer rate is small (e.g. data transfer
at 400 kbps with PCLK = 4 MHz), the characteristics of the digital noise filter may lead to the elimination of needed
signals as noise. In such cases, it is possible to disable the digital noise-filter circuit (by setting the ICFER.NFE bit to 0)
and use only the analog noise filter circuit.
SCL0/SDA0
D Q
input signal
T
IIC 
NFE : Digital noise filter circuit enable bit
NF[1:0] : Noise filter stage select bits
Figure 24.23 Block Diagram of Digital Noise Filter Circuit
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
Four-stage digital noise filter
D Q D Q D
T T T
Mismatch
Match
Com-
parator
Q D Q
T
NF[1:0]
2
24. I C-bus Interface (RIICa)
SCL0/SDA0
D Q
internal signal
T
PCLK
NFE
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