Renesas RX100 Series User Manual page 346

RX13T Group
Table 19.28 TIORL (MTU4)
Bit 3 Bit 2 Bit 1
IOC[3] IOC[2] IOC[1]
0 0 0
0 0 0
0 0 1
0 0 1
0 1 0
0 1 0
0 1 1
0 1 1
1 x 0
1 x 0
1 x 1
x: Don't care
Note 1. When the MTU4.TMDR1.BFB bit is set to 1 and MTU4.TGRC register is used as a buffer register, this setting is invalid and input
capture/output compare is not generated.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
Bit 0 Description
IOC[0] TGRC Register Function
0 Output compare register*
1
0
1
0
1
0
1
0 Input capture register*
1
x
19. Multi-Function Timer Pulse Unit 3 (MTU3c)
MTIOC4C Pin Function
1
Output prohibited
Initial output is low.
Low output at compare match.
Initial output is low.
High output at compare match.
Initial output is low.
Toggle output at compare match.
Output prohibited
Initial output is high.
Low output at compare match.
Initial output is high.
High output at compare match.
Initial output is high.
Toggle output at compare match.
1
Input capture at rising edge.
Input capture at falling edge.
Input capture at both edges.
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