Cpu; Features - Renesas RX100 Series User Manual

RX13T Group
2.

CPU

This MCU has the RX CPU as its core.
A variable-length instruction format has been adopted for the RX CPU. Allocating the more frequently used instructions
to the shorter instruction lengths facilitates the development of efficient programs that take up less memory.
The CPU has 73 basic instructions, 8 floating-point operation instructions, and nine DSP instructions, for a total of 90
instructions. It has 10 addressing modes and caters to register-to-register operations, register-to-memory operations,
immediate-to-register operations, immediate-to-memory operations, memory-to-memory transfer, and bitwise
operations. In a single cycle, high-speed calculation is attained for not just register-to-register operations, but also for
other types of combined instructions. The CPU includes an internal multiplier and an internal divider for high-speed
multiplication and division.
The RX CPU has a five-stage pipeline for processing instructions. The stages are instruction fetching, decoding,
execution, memory access, and write-back. In cases where pipeline processing is drawn-out by memory access,
subsequent operations may in fact be executed earlier. By adopting an "out-of-order completion" of this kind, instruction
execution is controlled to optimize the number of clock cycles.
2.1

Features

 Minimum instruction execution rate: One instruction per clock cycle
 Address space: 4-Gbyte linear
 Register set of the CPU
General purpose: Sixteen 32-bit registers
Control: Nine 32-bit registers
Accumulator: One 64-bit register
 Floating-point operation instructions: 8
 Basic instructions: 73 (arithmetic/logic instructions, data-transfer instructions, branch instructions, bit-manipulation
instructions, string-manipulation instructions, and system-manipulation instructions)
Relative branch instructions to suit branch distances
Variable-length instruction format (lengths from 1 to 8 bytes)
Short formats for frequently used instructions
 DSP instructions: 9
Supports 16-bit × 16-bit multiplication and multiply-and-accumulate operations.
Rounds the data in the accumulator.
 Addressing modes: 10
 Five-stage pipeline
Adoption of "out-of-order completion"
 Processor modes
A supervisor mode and a user mode are supported.
 Floating-point operation unit
Supports single-precision (32-bit) floating point
Supports data types and exceptions in conformance with the IEEE754 standard
 Data arrangement
Selectable as little endian or big endian
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
2. CPU
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