Spi Mode Register (Spmr) - Renesas RX100 Series User Manual

RX13T Group
23.2.19

SPI Mode Register (SPMR)

Address(es): SCI1.SPMR 0008 A02Dh, SCI5.SPMR 0008 A0ADh, SCI12.SPMR 0008 B30Dh
b7 b6
CKPH CKPOL
Value after reset: 0 0
Bit Symbol Bit Name
b0 SSE SSn# Pin Function Enable
b1 CTSE CTS Enable
b2 MSS Master Slave Select
b3 — Reserved
b4 MFF Mode Fault Flag
b5 — Reserved
b6 CKPOL Clock Polarity Select
b7 CKPH Clock Phase Select
Note 1. Writing to these bits is only possible when the RE and TE bits in the SCR are 0 (both serial transmission and reception are
disabled).
Note 2. Only 0 can be written to these bits, which clears the flag.
SPMR is used to select the extension settings in asynchronous and clock synchronous modes.
SSE Bit (SSn# Pin Function Enable)
Set this bit to 1 if the SSn# pin is to be used in control of transmission and reception (in simple SPI mode). Set this bit to
0 in any other mode. Furthermore, even for usage in simple SPI mode, the SSn# pin on the master side is not required to
control reception and transmission when master mode (SCR.CKE[1:0] = 00b and MSS = 0) is selected and there is a
single master, so the setting for the SSE bit is 0. Do not set both the SSE and CTSE bits to enabled (even if this setting is
made, operation is the same as that when these bits are set to 0).
CTSE Bit (CTS Enable)
Set this bit to 1 if the SSn# pin is to be used for inputting of the CTS control signal to control of transmission and
reception. The RTS signal is output when this bit is set to 0. Set this bit to 0 in smart card interface mode, simple SPI
2
mode, and simple I C mode. Do not set both the CTSE and SSE bits to enabled (even if this setting is made, operation is
the same as that when these bits are set to 0).
MSS Bit (Master Slave Select)
This bit selects between master and slave operation in simple SPI mode. When the MSS bit is set to 1, data is received
through the SMOSIn pin and transmitted through the SMISOn pin.
Set this bit to 0 in modes other than simple SPI mode.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b5 b4 b3 b2
— MFF — MSS CTSE
0 0 0 0
Description
0: SSn# pin function is disabled.
1: SSn# pin function is enabled.
0: CTS function is disabled (RTS output function is enabled).
1: CTS function is enabled.
0: Transmission is through the SMOSIn pin and reception is
1: Reception is through the SMOSIn pin and transmission is
This bit is read as 0. The write value should be 0.
0: No mode fault error
1: Mode fault error
This bit is read as 0. The write value should be 0.
0: Clock polarity is not inverted.
1: Clock polarity is inverted.
0: Clock is not delayed.
1: Clock is delayed.
23. Serial Communications Interface (SCIg, SCIh)
b1 b0
SSE
0 0
through the SMISOn pin (master mode).
through the SMISOn pin (slave mode).
R/W
R/W* 1
1
R/W*
1
R/W*
R/W
2
R/W*
R/W
1
R/W*
1
R/W*
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