Status Clear Register (Stcr); Control Field 0 Data Register (Cf0Dr) - Renesas RX100 Series User Manual

RX13T Group
23.2.28

Status Clear Register (STCR)

Address(es): SCI12.STCR 0008 B328h
b7 b6
— —
Value after reset: 0 0
Bit Symbol Bit Name
b0 BFDCL BFDF Clear
b1 CF0MCL CF0MF Clear
b2 CF1MCL CF1MF Clear
b3 PIBDCL PIBDF Clear
b4 BCDCL BCDF Clear
b5 AEDCL AEDF Clear
b7, b6 — Reserved
23.2.29

Control Field 0 Data Register (CF0DR)

Address(es): SCI12.CF0DR 0008 B329h
b7 b6
0 0
Value after reset:
The CF0DR register is an 8-bit readable and writable register that holds a value for comparison with Control Field 0.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b5 b4 b3 b2
AEDCL BCDCL PIBDC CF1MC
L L
0 0 0 0
Description
Setting this bit to 1 clears the STR.BFDF flag. This bit is read as 0.
Setting this bit to 1 clears the STR.CF0MF flag. This bit is read as 0.
Setting this bit to 1 clears the STR.CF1MF flag. This bit is read as 0.
Setting this bit to 1 clears the STR.PIBDF flag. This bit is read as 0.
Setting this bit to 1 clears the STR.BCDF flag. This bit is read as 0.
Setting this bit to 1 clears the STR.AEDF flag. This bit is read as 0.
These bits are read as 0. The write value should be 0.
b5 b4 b3 b2
0 0 0 0
23. Serial Communications Interface (SCIg, SCIh)
b1 b0
CF0MC
BFDCL
L
0 0
b1 b0
0 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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