Renesas RX100 Series User Manual page 568

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RPES[1:0] Bits (Window End Position Select)

These bits select 75%, 50%, 25% or 0% of the count period for the window end position of the counter. The window end

position should be a value smaller than the window start position (window start position > window end position). If the

window end position is greater than the window start position, only the window start position setting is enabled.

The counter values for the window start and end positions selected by setting the RPSS[1:0] and RPES[1:0] bits change

depending on the TOPS[1:0] bit setting.

Table 22.3 lists the counter values for the window start and end positions corresponding to TOPS[1:0] bit values.

Relationship between Timeout Period and Window Start and End Counter Values

TOPS[1:0] Bits

RPSS[1:0] Bits (Window Start Position Select)

These bits select a counter window start position from 100%, 75%, 50%, or 25% of the count period (100% when the

count starts and 0% when the counter underflows). The interval between the window start position and window end

position is the refresh-permitted period and the other periods are refresh-prohibited periods.

Figure 22.2 shows the relationship between of the RPSS[1:0] and RPES[1:0] bit setting and the refresh-permitted and

refresh-prohibited periods.

RPSS[1:0] Bits

If window end setting is greater than or equal to window start setting,

the window end setting is set to 0%.

RPSS[1:0] and RPES[1:0] Bit Settings and the Refresh-Permitted Period

R01UH0822EJ0100 Rev.1.00

Jul 31, 2019

Timeout Period

Counter Value

RPES[1:0] Bits

22. Independent Watchdog Timer (IWDTa)

Window Start and End Counter Value

Refresh-permitted period

Refresh-prohibited period

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