Address Match Detection; Slave-Address Match Detection - Renesas RX100 Series User Manual

RX13T Group
24.7

Address Match Detection

The RIIC can set three unique slave addresses in addition to the general call address and host address, and also can set 7-
bit or 10-bit slave addresses.
24.7.1

Slave-Address Match Detection

The RIIC can set three unique slave addresses, and has a slave address detection function for each unique slave address.
When the ICSER.SARyE bit (y = 0 to 2) is set to 1, the slave addresses set in registers SARUy and SARLy (y = 0 to 2)
can be detected.
When the RIIC detects a match of the set slave address, the corresponding ICSR1.AASy flag (y = 0 to 2) is set to 1 at the
rising edge of the ninth SCL clock cycle, and the ICSR2.RDRF flag or the ICSR2.TDRE flag is set to 1 by the following
R/W# bit. This causes a receive data full interrupt (RXI) or transmit data empty interrupt (TXI) to be generated. The
AASy flag is used to identify which slave address has been specified.
Figure 24.24 to Figure 24.26 show the AASy flag set timing in three cases.
[7-bit address format: Slave reception]
S 1 2
SCL0
SDA0
BBSY
AASy
TRS
TDRE
RDRF
[7-bit address format: Slave transmission]
S 1 2
SCL0
SDA0
BBSY
AASy
TRS
TDRE
RDRF
Figure 24.24 AASy Flag Set Timing with 7-Bit Address Format Selected
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
3 4 5 6 7 8
7-bit slave address
W
Receive data (7-bit address)
(Dummy read [7-bit address])
3 4 5 6 7 8
7-bit slave address R
Write data to ICDRT
register (DATA 1)
9 1 2 3 4 5
Data (DATA 1)
ACK
Address match
Read ICDRR register
9 1 2 3 4 5
ACK Data (DATA 1)
Address match
Transmit data (DATA 1)
Write data to ICDRT
register (DATA 2)
2
24. I C-bus Interface (RIICa)
6 7 8 9 1 2
ACK
Receive data (DATA 1)
Read ICDRR register
(DATA 1)
6 7 8 9 1 2
ACK
Transmit data (DATA 2)
Write data to ICDRT
register (DATA 3)
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3 4 5
Data (DATA 2)
3 4 5
Data (DATA 2)