Internal Peripheral Buses - Renesas RX100 Series User Manual

RX13T Group
15.2.4

Internal Peripheral Buses

Connection of peripheral modules to the internal peripheral buses is as described in Table 15.4 .
Table 15.4 Connection of Peripheral Modules to the Internal Peripheral Buses
Type of Bus
Internal peripheral bus 1
Internal peripheral bus 2
Internal peripheral bus 3
Internal peripheral bus 6
Requests for bus mastership from the CPU (internal main bus 1) and other bus masters (internal main bus 2) are
arbitrated through internal peripheral buses 1 to 3 and 6.
The priority order of the two internal main buses can be set using the bus priority control register (BUSPRI). The priority
order can be set with the internal peripheral bus 1 priority control bits (BUSPRI.BPIB[1:0]), internal peripheral buses 2
and 3 priority control bits (BUSPRI.BPGB[1:0]), and internal peripheral bus 6 priority control bits (BUSPRI.BPFB[1:0])
for the corresponding internal peripheral buses. When the priority order is fixed, internal main bus 2 has priority over
internal main bus 1. When the priority order is toggled, a bus has a lower priority when the request of that bus is
accepted.
The order of accepting requests may change depending on the BUSPRI setting (see Figure 15.2 ).
Priority order fixed:
Internal main bus 1
Internal main bus 2
Priority order toggled:
Internal main bus 1
Internal main bus 2
Figure 15.2 Priority Order Between Internal Peripheral Bus Accesses
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
Peripheral Modules
DTC, interrupt controller, and bus error monitoring section
Peripheral modules other than those connected to internal peripheral buses 1 and 3
CMPC
ROM (P/E)/E2 DataFlash
(R11) (R11)
R21
(R11)
R21 (R22)
(1), (2) : The priority order does not change because the priority of the accepted request is low.
(R11) R11 R12
R22 R23
R11 (R12) R12 R13
(1)
R22
(*)
*
(R13) (R13) R13
R24 R25
(2)
R23 R24 R25
Request issued; not accepted
Request issued; accepted
No request issued
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15. Buses