Renesas RX100 Series User Manual page 583

RX13T Group
Table 23.1 SCIg Specifications (2/2)
Item
Clock synchronous Data length
mode
Receive error detection
Hardware flow control
Smart card interface Error processing
mode
Data type
2
Simple I C mode Transfer format
Operating mode
Transfer rate
Noise cancellation
Simple SPI bus Data length
Detection of errors
SS input pin function
Clock settings
Bit rate modulation function
2
Note 1. In simple I C mode, only MSB first is available.
Table 23.2 SCIh Specifications (1/2)
Item
Serial communication modes
Transfer speed
Full-duplex communications
I/O pins
Data transfer
Interrupt sources
Low power consumption function
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
Description
8 bits
Overrun error
CTSn# and RTSn# pins can be used in controlling transmission/reception.
An error signal can be automatically transmitted when detecting a parity error during
reception
Data can be automatically retransmitted when receiving an error signal during
transmission
Both direct convention and inverse convention are supported.
2
I C-bus format
Master (single-master operation only)
Fast mode is supported (refer to section 23.2.11, Bit Rate Register (BRR) to set the
transfer rate).
The signal paths from input on the SSCLn and SSDAn pins incorporate digital noise
filters, and the interval for noise cancellation is adjustable.
8 bits
Overrun error
Applying the high level to the SSn# pin can cause the output pins to enter the
high-impedance state.
Four kinds of settings for clock phase and clock polarity are selectable.
Correction of outputs from the on-chip baud rate generator can reduce errors.
Description
 Asynchronous
 Clock synchronous
 Smart card interface
 Simple I
2
C-bus
 Simple SPI bus
Bit rate specifiable with the on-chip baud rate generator.
Transmitter: Continuous transmission possible using double-buffer structure.
Receiver: Continuous reception possible using double-buffer structure.
Refer to Table 23.4 to Table 23.7.
Selectable as LSB first or MSB first transfer*
Transmit end, transmit data empty, receive data full, and receive error
Completion of generation of a start condition, restart condition, or stop condition (for simple
2
I C mode)
Module stop state can be set.
23. Serial Communications Interface (SCIg, SCIh)
1
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