Renesas RX100 Series User Manual page 816

RX13T Group
Table 26.5 Relationship between DBLANS[4:0] Bits Settings and Double Trigger Enabled Channels
DBLANS[4:0]
00000b
00001b
00010b
00011b
00100b
00101b
00110b
00111b
Note: Duplication cannot be selected for the A/D conversion data of self-diagnosis and internal reference voltage.
GBADIE Bit (Group B Scan End Interrupt Enable)
The GBADIE bit enables or disables group B scan end interrupt in group scan mode.
DBLE Bit (Double Trigger Mode Select)
Double trigger mode has a function to store the resulting data of A/D conversion started by the first and second
synchronous triggers into separate registers.
When double trigger mode is selected, the channels specified in the ADANSA0 register are invalid and the channel
selected by the DBLANS[4:0] bits is effective instead. Double trigger mode can be only operated by the synchronous
trigger selected by the ADSTRGR.TRSA[5:0] bits. Do not generate an asynchronous or software trigger. The A/D
conversion results started by the first trigger are stored into the A/D data register y and those started by the second trigger
are stored into the A/D data duplication register. In this case, if the ADIE bit is set to 1, the interrupt is generated not
upon completion of the first conversion but upon completion of the second conversion.
In continuous scan mode, double trigger mode should not be selected. In addition, double trigger mode should not be
used for self-diagnosis or conversion of the internal reference voltage. When using double trigger mode in group scan
mode, A/D conversion of the internal reference voltage should not be selected for group A.
The DBLE bit should be set after the ADST bit has been set to 0.
EXTRG Bit (Trigger Select)
The EXTRG bit selects the synchronous trigger or the asynchronous trigger as the trigger for starting A/D conversion.
In group scan mode, the setting of this bit is valid for the selected trigger of group A.
For groups B and C, A/D conversion is started by the selected synchronous trigger regardless of this bit setting.
TRGE Bit (Trigger Start Enable)
The TRGE bit enables or disables A/D conversion by the synchronous trigger and the asynchronous trigger.
This bit should be set to 1 in group scan mode.
ADIE Bit (Scan End Interrupt Enable)
The ADIE bit enables or disables the A/D scan end interrupt (S12ADI) in scans except for groups B and C scan in group
scan mode.
With double trigger mode deselected, the A/D scan conversion end is generated after the first scan is completed if the
ADIE bit is set to 1.
With double trigger mode selected, the A/D scan conversion end is generated after the second scan is completed if the
ADIE bit is set to 1 as long as the scan is started by the synchronous trigger selected by the ADSTRGR.TRSA[5:0] bits.
When scan is started by a software trigger, even with double trigger mode selected, the A/D scan conversion end
interrupt is generated if the ADIE bit is set to 1 when the scan is completed.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
Duplication Channel
AN000
AN001
AN002
AN003
AN004
AN005
AN006
AN007
26. 12-Bit A/D Converter (S12ADF)
Page 816 of 1041