Timer A/D Converter Start Request Control Register (Tadcr) - Renesas RX100 Series User Manual

RX13T Group
19.2.34

Timer A/D Converter Start Request Control Register (TADCR)

Address(es): MTU4.TADCR 0009 5240h
b15 b14
BF[1:0]
Value after reset: 0 0
Bit Symbol Bit Name
b0 ITB4VE TCIV4 Interrupt Skipping Link
Enable*
b1 ITB3AE TGIA3 Interrupt Skipping Link
Enable*
b2 ITA4VE TCIV4 Interrupt Skipping Link
Enable*
b3 ITA3AE TGIA3 Interrupt Skipping Link
Enable*
b4 DT4BE Down-Count TRG4BN Enable*
b5 UT4BE Up-Count TRG4BN Enable
b6 DT4AE Down-Count TRG4AN Enable*
b7 UT4AE Up-Count TRG4AN Enable
b13 to b8 — Reserved
b15, b14 BF[1:0] MTU4.TADCOBRA/TADCOBRB
Transfer Timing Select
Note: MTU4.TADCR must not be accessed in 8 bits; it should be accessed in 16 bits.
Note 1. Set to 0 when interrupt skipping is disabled (the T3AEN and T4VEN bits in TITCR1A are set to 0 or the T3ACOR and T4VCOR
bits in TITCR1A are set to 0).
Note 2. If link with interrupt skipping is enabled while interrupt skipping is disabled, A/D converter start requests will not be issued.
Note 3. Set to 0 when complementary PWM mode is not selected.
TADCR enables or disables A/D converter start requests and specifies whether to link A/D converter start requests with
interrupt skipping function.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b13 b12 b11 b10
— — — —
0 0 0 0
1, 2, 3
* *
1, 2, 3
* *
1, 2, 3
* *
1, 2, 3
* *
3
3
19. Multi-Function Timer Pulse Unit 3 (MTU3c)
b9 b8 b7 b6
— — UT4AE DT4AE UT4BE DT4BE ITA3AE ITA4VE ITB3AE ITB4VE
0 0 0 0
Description
0: A/D converter start request signal TRG4BN and TCIV4
interrupt skipping 1 are not linked
1: A/D converter start request signal TRG4BN and TCIV4
interrupt skipping 1 are linked
0: A/D converter start request signal TRG4BN and TGIA3
interrupt skipping 1 are not linked
1: A/D converter start request signal TRG4BN and TGIA3
interrupt skipping 1 are linked
0: A/D converter start request signal TRG4AN and TCIV4
interrupt skipping 1 are not linked
1: A/D converter start request signal TRG4AN and TCIV4
interrupt skipping 1 are linked
0: A/D converter start request signal TRG4AN and TGIA3
interrupt skipping 1 are not linked
1: A/D converter start request signal TRG4AN and TGIA3
interrupt skipping 1 are linked
0: A/D converter start requests (TRG4BN) disabled during
MTU4.TCNT down-count operation
1: A/D converter start requests (TRG4BN) enabled during
MTU4.TCNT down-count operation
0: A/D converter start requests (TRG4BN) disabled during
MTU4.TCNT up-count operation
1: A/D converter start requests (TRG4BN) enabled during
MTU4.TCNT up-count operation
0: A/D converter start requests (TRG4AN) disabled during
MTU4.TCNT down-count operation
1: A/D converter start requests (TRG4AN) enabled during
MTU4.TCNT down-count operation
0: A/D converter start requests (TRG4AN) disabled during
MTU4.TCNT up-count operation
1: A/D converter up requests (TRG4AN) enabled during
MTU4.TCNT down-count operation
These bits are read as 0. The write value should be 0.
Refer to Table 19.41 for details.
These bits specify the transfer timing from MTU4.TADCOBRA
and MTU4.TADCOBRB to MTU4.TADCORA and
MTU4.TADCORB.
b5 b4 b3 b2
0 0 0 0
Page 378 of 1041
b1 b0
0 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W