Bus Error Monitoring Section; Type Of Bus Error; Illegal Address Access; Timeout - Renesas RX100 Series User Manual

RX13T Group
15.4

Bus Error Monitoring Section

The bus error monitoring section monitors the individual areas for bus errors, and when a bus error occurs, the error is
indicated to the bus master.
15.4.1

Type of Bus Error

There are two types of bus error: illegal address access and timeout.
Illegal address access is the detection of illegal access to an area, and time-out is the detection of a bus-access operation
not being completed within 768 cycles.
15.4.1.1

Illegal Address Access

When the illegal address access detection enable bit (IGAEN) in the bus error monitoring enable register (BEREN) is set
to 1, access to an illegal address area leads to illegal address access errors.
The address ranges where access will lead to illegal address access errors are listed in Table 15.5 .
15.4.1.2

Timeout

When the timeout detection enable bit in the bus error monitoring enable register is enabled (BEREN.TOEN = 1), bus
access that is not completed within 768 cycles leads to a timeout error.
 Internal peripheral buses (2 and 3): Bus access is not completed within 768 peripheral module clock (PCLKB)
cycles from the start of the access.
If a timeout error occurs, accesses from the bus master are not accepted for 256 PCLKB cycles.
 Internal peripheral bus (6): Bus access is not completed within 768 FlashIF clock (FCLK) cycles from the start of
the access.
If a timeout error occurs, accesses from the bus master are not accepted for 256 FCLK cycles.
15.4.2

Operations When a Bus Error Occurs

When a bus error occurs, the error is indicated to the CPU. Operation is not guaranteed when a bus error occurs.
 Bus error indication to the CPU
An interrupt is generated. The ICU.IERn register can specify whether to generate an interrupt in the case of a bus
error.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
15. Buses
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