Operation; Count Operation In Each Start Mode; Register Start Mode - Renesas RX100 Series User Manual

RX13T Group
22.3

Operation

22.3.1

Count Operation in Each Start Mode

Select the IWDT start mode by setting the IWDTSTRT bit in option function select register 0 (OFS0).
When the OFS0.IWDTSTRT bit is 1 (register start mode), the IWDTCR, IWDTRCR, and IWDTCSTPR registers are
enabled, and counting is started by refresh operation (writing) to the IWDTRR register. When the OFS0.IWDTSTRT bit
is 0 (auto-start mode), the setting of the OFS0 register is enabled, and counting automatically starts after reset.
22.3.1.1

Register Start Mode

When the OFS0.IWDTSTRT bit in option function select register 0 is 1, register start mode is selected, and the
IWDTCR, IWDTRCR, and IWDTCSTPR registers are enabled.
After a reset is released, set the clock divide ratio, window start and end positions, and timeout period in the IWDTCR
register, the reset output or interrupt request output in the IWDTRCR register, and the counter stop control at transitions
to low power consumption states in the IWDTCSTPR register. Then refresh the counter to start counting down from the
value selected by setting the IWDTCR.TOPS[1:0] bits.
Thereafter, as long as the program continues normal operation and the counter is refreshed in the refresh-permitted
period, the value in the counter is re-set each time the counter is refreshed and counting down continues. The IWDT does
not output the reset signal as long as this continues. However, if the counter underflows because the counter cannot be
refreshed due to a program runaway, or if a refresh error occurs because the counter was refreshed outside the refresh-
permitted period, the IWDT outputs a reset signal or a non-maskable interrupt request (WUNI). Set the
IWDTRCR.RSTIRQS bit to select either reset output or interrupt request output.
Figure 22.3 shows an example of operation under the following conditions.
 Register start mode (OFS0.IWDTSTRT = 1)
 Reset output is enabled (IWDTRCR.RSTIRQS = 1)
 The window start position is 75% (IWDTCR.RPSS[1:0] = 10b)
 The window end position is 25% (IWDTCR.RPES[1:0] = 10b)
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
22. Independent Watchdog Timer (IWDTa)
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