Timer Buffer Transfer Set Register (Tbtera) - Renesas RX100 Series User Manual

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19.2.30

Timer Buffer Transfer Set Register (TBTERA)

Address(es): MTU.TBTERA 0009 5232h
b7
b6
Value after reset:
0
0
Bit
Symbol
b1, b0
BTE[1:0]
b7 to b2
Note 1. Applicable buffer registers (TBTERA):
MTU3.TGRC, MTU3.TGRD, MTU4.TGRC, MTU4.TGRD, and TCBRA
TBTERA enables or disables transfer from the buffer registers used in complementary PWM mode to the temporary
registers, and specify whether to link the transfer with interrupt skipping 1 operation.
Table 19.40
Setting of TBTERA.BTE[1:0] Bits
Bit 1
Bit 0
BTE[1]
BTE[0]
0
0
0
1
1
0
1
1
Note 1. Data is transferred according to the MD3 to MD0 bit setting in TMDR1. For details, refer to section 19.3.8, Complementary PWM
Mode.
Note 2. When interrupt skipping is disabled the T3AEN and T4VEN bits are set to 0 in the timer interrupt skipping set register (TITCR1A)
or the skipping count set bits (T3ACOR and T4VCOR) in TITCR1A are set to 0), be sure to disable link of buffer transfer with
interrupt skipping (set the BTE1 bit in the timer buffer transfer set register (TBTERA) to 0). If link with interrupt skipping is
enabled while interrupt skipping is disabled, buffer transfer will not be performed.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b5
b4
b3
b2
0
0
0
0
Bit Name
Buffer Transfer Disable and
Interrupt Skipping Link Setting
Reserved
Description
Enables transfer from the buffer registers to the temporary registers*
transfer with interrupt skipping function 1.
Disables transfer from the buffer registers to the temporary registers.
Links transfer from the buffer registers to the temporary registers with interrupt skipping function
2
1.*
Setting prohibited
19. Multi-Function Timer Pulse Unit 3 (MTU3c)
b1
b0
BTE[1:0]
0
0
Description
These bits enable or disable transfer from the buffer registers*
used in complementary PWM mode to the temporary registers,
and specify whether to link the transfer with interrupt skipping
function 1.
For details, refer to Table 19.40.
These bits are read as 0. The write value should be 0.
R/W
1
R/W
R/W
1
and does not link the
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