Renesas RX100 Series User Manual page 64

RX13T Group
(5) WB stage (write-back stage)
The operation result and the data read from memory are written to the register (RW) in the WB stage. The data read from
memory and the other type of data, such as the operation result, can be written to the register in the same clock cycles.
Figure 2.6 shows the pipeline configuration and its operation.
Pipeline stage
Execution processing
Figure 2.6 Pipeline Configuration and its Operation
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
One cycle
IF stage D stage
BYP
IF DEC
RF
M stage
E stage M1 stage
OP
OA1
2. CPU
M2 stage WB stage
RW
OA2
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