Renesas RX100 Series User Manual page 342

32-bit mcu
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RX13T Group
Table 19.20
TIORL (MTU4)
Bit 7
Bit 6
Bit 5
IOD[3]
IOD[2]
IOD[1]
0
0
0
0
0
0
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
x
0
1
x
0
1
x
1
x: Don't care
Note 1. When the MTU4.TMDR1.BFB bit is set to 1 and MTU4.TGRD register is used as a buffer register, this setting is invalid and input
capture/output compare is not generated.
Table 19.21
TIORH (MTU0)
Bit 3
Bit 2
Bit 1
IOA[3]
IOA[2]
IOA[1]
0
0
0
0
0
0
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
1
0
0
1
0
1
1
1
x
x: Don't care
Note 1. When PCLKB/1 is selected as the count clock for MTU1, MTU0 input capture is not generated. Do not select PCLKB/1 as the
count clock for MTU1.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
Bit 4
Description
IOD[0]
TGRD Register Function
0
Output compare register*
1
0
1
0
1
0
1
0
Input capture register*
1
x
Bit 0
Description
IOA[0]
TGRA Register Function
0
Output compare register
1
0
1
0
1
0
1
0
Input capture register
1
x
x
19. Multi-Function Timer Pulse Unit 3 (MTU3c)
MTIOC4D Pin Function
1
Output prohibited
Initial output is low.
Low output at compare match.
Initial output is low.
High output at compare match.
Initial output is low.
Toggle output at compare match.
Output prohibited
Initial output is high.
Low output at compare match.
Initial output is high.
High output at compare match.
Initial output is high.
Toggle output at compare match.
1
Input capture at rising edge.
Input capture at falling edge.
Input capture at both edges.
MTIOC0A Pin Function
Output prohibited
Initial output is low.
Low output at compare match.
Initial output is low.
High output at compare match.
Initial output is low.
Toggle output at compare match.
Output prohibited
Initial output is high.
Low output at compare match.
Initial output is high.
High output at compare match.
Initial output is high.
Toggle output at compare match.
Input capture at rising edge.
Input capture at falling edge.
Input capture at both edges.
Capture input source is the clock source for counting in MTU1.
Input capture on counting up or down by MTU1.TCNT (LWA = 0) or
MTU1.TCNTLW (LWA = 1).*
1
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