Renesas RX100 Series User Manual page 686

RX13T Group
Initialization
Start of transmission
Simultaneously set the SIMR3.IICSTAREQ
bit to 1 and the SIMR3.IICSCLS[1:0] and
IICSDAS[1:0] bits to 01b
STI interrupt?
Set the SIMR3.IICSTIF to 0, and set the
SIMR3.IICSCLS[1:0] and IICSDAS[1:0] bits to
Write the slave address and value for the
R/W bit in TDR
TXI interrupt?
SISR.IICACKR = 0?
Write transmit data in TDR
TXI interrupt?
No
All data transmitted?
Simultaneously set the SIMR3.IICSTPREQ
bit to 1 and the SIMR3.IICSCLS[1:0] and
IICSDAS[1:0] bits to 01b
STI interrupt?
Set the SIMR3.IICSTIF to 0, and set the
SIMR3.IICSCLS[1:0] and IICSDAS[1:0] bits to
Figure 23.53 Example of the Procedure for Master Transmission Operations in Simple I
(with Transmission Interrupts and Reception Interrupts in Use)
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
No
Yes
00b
No
Yes
No
Yes
No
Yes
Yes
No
Yes
11b
End
23. Serial Communications Interface (SCIg, SCIh)
[ 1 ] Initialization for simple I
[ 1 ]
For transmission, set the SCR.RIE bit to 0 (RXI and ERI
interrupts requests are disabled)
[ 2 ] Generate a start condition.
[ 3 ] Writing to TDR:
Writing the slave address and value for the R/W bit to TDR.
[ 2 ]
[ 4 ] Confirming ACK response from the slave address:
Check the SISR.IICACKR bit. If its value is 0, it is indicated
that the slave device responded with ACK and operations
proceed. If its value is 1, it is indicated that there was no
response from a slave device so the next transition is to
generation of the stop condition.
[ 5 ] Steps for continuing with serial transmission:
When transmission is to continue, write further transmit data
to TDR. Except for the first data to be transmitted, a TXI
request can activate the DTC to handle writing of data to
TDR.
[ 3 ]
[ 6 ] Generation of a stop condition.
If 10-bit slave addresses are in use, processing of [3] and [4]
[ 4 ] is repeated twice.
2
Note: In simple I C mode, the TXI interrupt request is generated
when communication is completed, unlike the timing during
clock synchronous transmission.
[ 5 ]
[ 6 ]
2
C mode
2
C Mode
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