A/D Conversion In Double Trigger Mode - Renesas RX100 Series User Manual

RX13T Group
26.3.2.6

A/D Conversion in Double Trigger Mode

In single scan mode with double trigger mode, single scan operation started by synchronous trigger is performed twice as
below.
Self-diagnosis should be deselected, and the internal reference voltage A/D conversion select bit
(S12AD.ADEXICR.OCSA) should be set to 0.
Duplication of A/D conversion data is enabled by setting the channel numbers to be duplicated to the
ADCSR.DBLANS[4:0] bits and setting the ADCSR.DBLE bit to 1. When the ADCSR.DBLE bit is set to 1, channel
selection using the ADANSA0 register is invalid. In double trigger mode, synchronous triggers should be selected using
the ADSTRGR.TRSA[5:0] bits, the ADCSR.EXTRG bit should be set to 0, and the ADCSR.TRGE bit should be set to
1. Software trigger should not be used.
(1) When the ADCSR.ADST bit is set to 1 (A/D conversion start) by synchronous trigger input, A/D conversion is
started on the single channel selected by the ADCSR.DBLANS[4:0] bits.
(2) When A/D conversion is completed, the A/D conversion result is stored into the corresponding A/D data register
(ADDRy).
(3) The ADCSR.ADST bit is automatically cleared to 0 and the 12-bit A/D converter enters a wait state. Here, a scan
end interrupt request is not generated irrespective of the ADCSR.ADIE bit setting (interrupt generation upon
scanning completion enabled).
(4) When the ADCSR.ADST bit is set to 1 (A/D conversion start) by the second trigger input, A/D conversion is started
on the single channel selected by the ADCSR.DBLANS[4:0] bits.
(5) When A/D conversion is completed, the A/D conversion result is stored into the A/D data duplication register
(ADDBLDR), which is exclusively used in double trigger mode.
(6) If the ADCSR.ADIE bit is 1 (interrupt generation upon scanning completion enabled), a scan end interrupt request
is generated.
(7) The ADCSR.ADST bit remains 1 (A/D conversion start) during A/D conversion, and is automatically cleared to 0
when A/D conversion is completed. Then the 12-bit A/D converter enters a wait state.
Synchronous
trigger
A/D conversion
ADST
started
Channel 3
Waiting for conversion
(AN003)
ADDR3
ADDBLDR
Scan end
interrupt
Figure 26.7 Example of Operation in Single Scan Mode (Double Trigger Mode Selected; AN003 Duplicated)
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
A/D conversion
performed once
Set
(1)
(3)
A/D conversion time
A/D conversion 1 Waiting for conversion
Stored (2)
A/D conversion result 1
26. 12-Bit A/D Converter (S12ADF)
A/D conversion
performed once
Set
(4)
A/D conversion time (7)
A/D conversion 2 Waiting for conversion
(5)
A/D conversion result 2
(6)
(6)
Interrupt generated
Page 844 of 1041