Register Descriptions; A/D Data Registers Y (Addry) (Y = 0 To 7); A/D Data Duplication Register (Addbldr); A/D Data Duplication Register A (Addbldra) - Renesas RX100 Series User Manual

RX13T Group
26.2

Register Descriptions

26.2.1

A/D Data Registers y (ADDRy) (y = 0 to 7),

A/D Data Duplication Register (ADDBLDR),

A/D Data Duplication Register A (ADDBLDRA),

A/D Data Duplication Register B (ADDBLDRB),

A/D Internal Reference Voltage Data Register (ADOCDR)

Address(es): S12AD.ADDR0 0008 9020h, S12AD.ADDR1 0008 9022h, S12AD.ADDR2 0008 9024h,
S12AD.ADDR3 0008 9026h, S12AD.ADDR4 0008 9028h, S12AD.ADDR5 0008 902Ah,
S12AD.ADDR6 0008 902Ch, S12AD.ADDR7 0008 902Eh, S12AD.ADDBLDR 0008 9018h,
S12AD.ADDBLDRA 0008 9084h, S12AD.ADDBLDRB 0008 9086h, S12AD.ADOCDR 0008 901Ch
b15 b14
Value after reset: 0 0
The ADDRy registers (y = 0 to 7) are 16-bit read-only registers which store the A/D conversion results.
The ADDBLDR register is a 16-bit read-only register used in double trigger mode. The ADDBLDR register stores the
results of A/D conversion when the conversion is started by the second trigger.
The ADDBLDRA and ADDBLDRB registers are 16-bit read-only registers that store the A/D conversion results in
response to the respective triggers during extended operation in double trigger mode.
The ADOCDR register is a 16-bit read-only register that stores the A/D conversion results of the internal reference
voltage.
The format of each register differs depending on the conditions below.
 Settings of the A/D data register format select bit (ADCER.ADRFMT) (flush-right or flush-left)
 Settings of the addition count select bits (ADADC.ADC[2:0]) (2-, 3-, 4-, or 16-time conversion)
 Settings of the average mode enable bit (ADADC.AVEE) (add or average)
The data formats for each given condition are shown below.
(1) When A/D-Converted Value Addition/Average Mode is Not Selected
 Flush-right format
The A/D-converted value is stored in bits 11 to 0. Bits 15 to 12 are read as 0.
 Flush-left format
The A/D-converted value is stored in bits 15 to 4. Bits 3 to 0 are read as 0.
(2) When A/D-Converted Average Mode is Selected
 Flush-right format
The mean value of the A/D-converted results of the same channel is stored in bits 11 to 0.
Bits 15 to 12 are read as 0.
 Flush-left format
The mean value of the A/D-converted results of the same channel is stored in bits 15 to 4.
Bits 3 to 0 are read as 0.
A/D-converted value average mode can be set only when 2- or 4-time conversion is selected in A/D-converted value
addition mode.
(3) When A/D-Converted Value Addition Mode is Selected
 Flush-right format (in A/D-converted value addition mode and when number of conversions is selected for 1 to 4
times)
The value added by the A/D-converted value of the same channel is stored in bits 13 to 0.
Bits 15 and 14 are read as 0.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b13 b12 b11 b10
0 0 0 0
b9 b8 b7 b6
0 0 0 0
26. 12-Bit A/D Converter (S12ADF)
b5 b4 b3 b2
0 0 0 0
Page 812 of 1041
b1 b0
0 0