Renesas RX100 Series User Manual page 223

RX13T Group
Figure 14.3 to Figure 14.5 show the interrupt signals of the interrupt controller. Note that the timings of the interrupts
with interrupt vector numbers 64 to 95 are different from those of other interrupts. For the IRQ pin interrupts with
interrupt vector numbers 64 to 79, "internal delay + 2 PCLK cycles" of delay is added after the IRQ pin input. For the
interrupts with interrupt vector numbers 80 to 95, "2 PCLK cycles" of delay is added.
If an interrupt signal is generated every clock cycle, the subsequent interrupts cannot be detected; secure two or more
clock cycles of the system clock between issuance of continuous interrupt requests.
While the IRn.IR flag is 1 after an interrupt request is generated, the interrupt request that is generated again will be
1
ignored. *
Figure 14.3 shows the timing for IRn.IR flag re-setting.
Note 1. When the transmission or reception interrupt of the SCI or RIIC is generated with the IRn.IR flag being 1, the
interrupt request is retained. After the IRn.IR flag is cleared to 0, the IRn.IR flag is set to 1 again by the retained
request. For details, see descriptions of the interrupts in section 23, Serial Communications Interface (SCIg,
SCIh) and section 24, I
Figure 14.3 Timing for IRn.IR Flag Re-Setting
If an interrupt is disabled after the IRn.IR flag is set to 1 (output of the interrupt request is disabled by the interrupt enable
bit of the relevant peripheral module), the IRn.IR flag is not affected but retains its state. Figure 14.4 shows operation
when the interrupt is disabled.
Interrupt request is enabled/disabled
Figure 14.4 Relationship between IRn.IR Flag Operation and Disabling of Interrupt Request
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
2
C-bus Interface (RIICa).
An interrupt request (2) is ignored while the IR flag in IRn is 1.
(1)
Interrupt signal
IRn.IR flag
Interrupt acceptance
Enabled
Interrupt signal
IRn.IR flag
(2) (3)
Interrupt acceptance
(1) (3)
Disabled
IRn.IR flag is not cleared even when the source is disabled
14. Interrupt Controller (ICUb)
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