Renesas RX100 Series User Manual page 443

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(n) Output Waveform Control at Synchronous Counter Clearing in Complementary PWM Mode

Setting the WRE bit in TWCRA to 1 suppresses initial output when synchronous counter clearing occurs in the Tb

interval (Tb2 interval) at the trough in complementary PWM mode and controls abrupt change in duty cycle at

synchronous counter clearing.

Initial output suppression through the WRE bit = 1 is applicable only when synchronous clearing occurs in the Tb2

interval as indicated by (10) or (11) in Figure 19.63 . When synchronous clearing occurs outside that interval, the initial

value specified by the OLSN and OLSP bits in TOCR1A is output. Even in the Tb2 interval, if synchronous clearing

occurs in the initial value output period (indicated by (1) in Figure 19.63 ) immediately after the counters start operation,

initial value output is not suppressed.

This function can be used in both channel combinations of MTU3 and MTU4. In MTU3 and MTU4, synchronous

clearing in any of MTU0 to MTU2 can cause counter clearing.

Counter start

Positive- phase

phase output

Figure 19.63

Timing for Synchronous Counter Clearing (MTU3 and MTU4)

R01UH0822EJ0100 Rev.1.00

Jul 31, 2019

19. Multi-Function Timer Pulse Unit 3 (MTU3c)

(Output waveform is active-low)

Page 443 of 1041