Interrupt Source Priority Register N (Iprn) (N = Interrupt Vector Number) - Renesas RX100 Series User Manual

RX13T Group
14.2.3

Interrupt Source Priority Register n (IPRn) (n = interrupt vector number)

Address(es): ICU.IPR000 0008 7300h to ICU.IPR255 0008 73FFh
b7 b6
— —
Value after reset: 0 0
Bit Symbol Bit Name
b3 to b0 IPR[3:0] Interrupt Priority Level Select
b7 to b4 — Reserved
Note 1. When the interrupt is specified as a fast interrupt, it can be issued even if the priority level is level 0.
For the correspondence between interrupt sources and IPRn registers, see Table 14.3, Interrupt Vector Table .
IPR[3:0] Bits (Interrupt Priority Level Select)
These bits specify the priority level of the corresponding interrupt source.
Priority levels specified by the IPR[3:0] bits are used only to determine the priority of interrupt requests to be transferred
to the CPU, and do not affect transfer requests to the DTC.
The CPU accepts only interrupt requests higher than the priority level specified by the IPL[3:0] bits in PSW, and handles
accepted interrupts.
If two or more interrupt requests are generated at the same time, their priority levels are compared with the value of the
IPR[3:0] bits. If interrupt requests of the same priority level are generated at the same time, an interrupt source with a
smaller vector number takes precedence.
These bits should be written to while an interrupt request is disabled (IERm.IENj bit = 0 (m = 02h to 1Fh, j = 0 to 7)).
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b5 b4 b3 b2
— — IPR[3:0]
0 0 0 0
b1 b0
0 0
Description
b3 b0
0 0 0 0: Level 0 (interrupt disabled)*
0 0 0 1: Level 1
0 0 1 0: Level 2
0 0 1 1: Level 3
0 1 0 0: Level 4
0 1 0 1: Level 5
0 1 1 0: Level 6
0 1 1 1: Level 7
1 0 0 0: Level 8
1 0 0 1: Level 9
1 0 1 0: Level 10
1 0 1 1: Level 11
1 1 0 0: Level 12
1 1 0 1: Level 13
1 1 1 0: Level 14
1 1 1 1: Level 15 (highest)
These bits are read as 0. The write value should be 0.
14. Interrupt Controller (ICUb)
R/W
R/W
1
R/W
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