Register Descriptions; Input Level Control/Status Register 1 (Icsr1) - Renesas RX100 Series User Manual

RX13T Group
20.2

Register Descriptions

The POE registers are initialized by a reset.
20.2.1

Input Level Control/Status Register 1 (ICSR1)

Address(es): POE.ICSR1 0008 C4C0h
b15 b14
— —
Value after reset: 0 0
Bit Symbol
b1, b0 POE0M[1:0]
b7 to b2 —
b8 PIE1
b11 to b9 —
b12 POE0F
b15 to b13 —
Note 1. Can be modified only once after a reset.
Note 2. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.
The ICSR1 register selects the POE0# pin input modes, controls the enable/disable of interrupts, and indicates status.
POE0M[1:0] Bits (POE0 Mode Select)
These bits select the input mode of the POE0# pin.
PIE1 Bit (Port Interrupt Enable 1)
This bit enables or disables interrupt requests when the POE0F flag is set to 1.
POE0F Flag (POE0 Flag)
This flag indicates that a high-impedance request has been input to the POE0# pin.
[Setting condition]
 When the input set by the POE0M[1:0] bits occurs at the POE0# pin
[Clearing condition]
 By writing 0 to the POE0F flag after reading POE0F = 1
When low-level sampling is set by the POE0M[1:0] bits, the high level needs to be input to the POE0# pin to write
0 to this flag.
For details, refer to section 20.3.7, Recover from High-Impedance State .
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b13 b12 b11 b10
— POE0F — —
0 0 0 0
Bit Name
POE0 Mode Select
Reserved
Port Interrupt Enable 1
Reserved
POE0 Flag
Reserved
b9 b8 b7 b6
— PIE1 — —
0 0 0 0
Description
b1 b0
0 0: Accepts a request on the falling edge of POE0# pin input.
0 1: Accepts a request when POE0# pin input has been sampled
16 times at PCLK/8 clock pulses and all are low level.
1 0: Accepts a request when POE0# pin input has been sampled
16 times at PCLK/16 clock pulses and all are low level.
1 1: Accepts a request when POE0# pin input has been sampled
16 times at PCLK/128 clock pulses and all are low level.
These bits are read as 0. The write value should be 0.
0: Interrupt requests disabled
1: Interrupt requests enabled
These bits are read as 0. The write value should be 0.
0: Indicates that a high-impedance request has not been input to
the POE0# pin.
1: Indicates that a high-impedance request has been input to the
POE0# pin.
These bits are read as 0. The write value should be 0.
20. Port Output Enable 3 (POE3C)
b5 b4 b3 b2
— — — —
0 0 0 0
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b1 b0
POE0M[1:0]
0 0
R/W
1
R/W*
R/W
R/W
R/W
R/(W)
* 2
R/W