24.12 Smbus Operation; Smbus Timeout Measurement - Renesas RX100 Series User Manual

RX13T Group

24.12 SMBus Operation

The RIIC is available for data communication conforming to the SMBus (Version 2.0). To perform SMBus
communication, set the ICMR3.SMBS bit to 1. To use the transfer rate within a range of 10 kbps to 100 kbps of the
SMBus specification, set the ICMR1.CKS[2:0] bits, the ICBRH register, and the ICBRL register. In addition, determine
the values of the ICMR2.DLCS bit and the ICMR2.SDDL[2:0] bits to meet the data hold time specification of 300 ns or
more. If the RIIC is used only as a slave device, the transfer rate setting is not necessary, whereas the ICBRL register
needs to be set to a value longer than the data setup time (250 ns).
For the SMBus device default address (1100 001b), use one of the slave address registers L0 to L2 (registers SARL0,
SARL1, and SARL2), and set the corresponding SARUy.FS bit (7-bit/10-bit address format select) (y = 0 to 2) to 0 (7-bit
address format).
When transmitting the UDID (Unique Device Identifier), set the ICFER.SALE bit to 1 to enable the slave arbitration-lost
detection function.
24.12.1

SMBus Timeout Measurement

(1) Measuring timeout of slave device
The following period (timeout interval: T
 From start condition to stop condition
To measure timeout for slave devices, measure the period from start condition detection to stop condition detection with
the MTU timer using a start condition detection interrupt (STI) and stop condition detection interrupt (SPI) of the RIIC.
The measured timeout period must be within the total clock low-level period [slave device] T
the SMBus specification.
If the time measured with the MTU exceeds the clock low-level detection timeout T
specification, the slave device must release the bus by writing 1 to the ICCR1.IICRST bit to issue an internal reset of the
RIIC. When an internal reset is issued, the RIIC stops driving the bus for the SCL0 pin and SDA0 pin and make the
SCL0/SDA0 pin outputs high-impedance, which releases the bus.
(2) Measuring timeout of master device
The following periods (timeout interval: T
 From start condition to acknowledge bit
 Between acknowledge bits
 From acknowledge bit to stop condition
To measure timeout for master devices, measure these periods with the MTU timer using a start condition detection
interrupt (STI), stop condition detection interrupt (SPI), and transmit end interrupt (TEI) or receive data full interrupt
(RXI) of the RIIC. The measured timeout period must be within the total clock low-level extended period (master
device) T : 10 ms (max.) of the SMBus specification, and the total of all T
LOW:MEXT
stop condition must be within T
For the ACK receive timing (rising edge of the ninth SCL clock cycle), monitor the ICSR2.TEND flag in master transmit
mode (master transmitter) and the ICSR2.RDRF flag in master receive mode (master receiver). For this reason, perform
bytewise transmit operation in master transmit mode, and hold the ICMR3.RDRFS bit 0 until the byte just before
reception of the final byte in master receive mode. While the RDRFS bit is 0, the RDRF flag is set to 1 at the rising edge
of the ninth SCL clock cycle.
If the period measured with the MTU exceeds the total clock low-level extended period (master device) T
ms (max.) of the SMBus specification or the total of measured periods exceeds the clock low-level detection timeout
T : 25 ms (min.) of the SMBus specification, the master device must stop the transaction by issuing a stop
TIMEOUT
condition. In master transmit mode, immediately stop the transmit operation (writing data to the ICDRT register).
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
) must be measured for slave devices in SMBus communication.
LOW:SEXT
) must be measured for master devices in SMBus communication.
LOW:MEXT
: 25 ms (max.).
LOW:SEXT
2
24. I C-bus Interface (RIICa)
: 25 ms (max.) of
LOW:SEXT
: 25 ms (min.) of the SMBus
TIMEOUT
from start condition to
LOW:MEXT
LOW:MEXT
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