Iwdt Reset Control Register (Iwdtrcr) - Renesas RX100 Series User Manual

RX13T Group
22.2.4

IWDT Reset Control Register (IWDTRCR)

Address(es): IWDT.IWDTRCR 0008 8036h
b7 b6
RSTIR
—
QS
Value after reset: 1 0
Bit Symbol
b6 to b0 —
b7 RSTIRQS
There are some restrictions on writing to the IWDTRCR register. For details, refer to section 22.3.2, Control over
Writing to the IWDTCR, IWDTRCR, and IWDTCSTPR Registers .
In auto-start mode, the IWDTRCR register setting are disabled, and the settings in option function select register 0
(OFS0) are enabled. The bit setting mode to the IWDTRCR register can also be made in the OFS0 register. For details,
refer to section 22.3.8, Correspondence between Option Function Select Register 0 (OFS0) and IWDT
Registers .
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b5 b4 b3 b2
— — — —
0 0 0 0
Bit Name
Reserved
Reset Interrupt Request Select
22. Independent Watchdog Timer (IWDTa)
b1 b0
— —
0 0
Description
These bits are read as 0. Writing to these bits has no effect.
0: Non-maskable interrupt request output is enabled.
1: Reset output is enabled.
R/W
R
R/W
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