Dtc Operation Register (Dtcor) - Renesas RX100 Series User Manual

RX13T Group
16.2.14

DTC Operation Register (DTCOR)

Address(es): DTC.DTCOR 0008 2414h
b7 b6
— —
Value after reset: 0 0
Bit Symbol Bit Name
b0 SQTFRL Sequence Transfer Terminate
b7 to b1 — Reserved
The DTCOR register sets the operation of the DTC module.
SQTFRL Bit (Sequence Transfer Terminate)
Setting the SQTFRL bit to 1 terminates the sequence transfer in progress.
When the DTCSQE.ESPSEL bit is 1 (Sequence transfer is enabled), follow the procedure shown in Figure 16.2 to
terminate the sequence transfer.
Writing 1 to the bit, while no sequence transfer is performed, have no effect.
Disable the DTC transfer request
by the corresponding interrupt
Wait for completion of the
corresponding data transfer
which is in progress
Terminate the DTC sequence
transfer
Figure 16.2 Procedure to Terminate Sequence Transfer
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b5 b4 b3 b2
— — — —
0 0 0 0
No
b1 b0
SQTFR
—
L
0 0
Description
Writing 1 to this bit terminates the sequence transfer in
progress. This bit is read as 0.
These bits are read as 0. The write value should be 0.
Start
IERm.IENj (interrupt request enable bit) = 0
DTCSTS.ACT = 1?
Yes
DTCSTS.VECN[7:0] = DTCSQE.VECN[7:0]?
No
DTCOR.SQTFRL = 1
End
16. Data Transfer Controller (DTCb)
Yes
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