Timer Period Buffer Register (Tcbra); Timer Dead Time Data Register (Tddra) - Renesas RX100 Series User Manual

RX13T Group
19.2.27

Timer Period Buffer Register (TCBRA)

Address(es): MTU.TCBRA 0009 5222h
b15 b14
Value after reset: 1 1
Note: TCBRA must not be accessed in 8 bits; it should be accessed in 16 bits.
TCBRA is a 16-bit readable/writable register, used only in complementary PWM mode, that function as buffer register
for TCDRA. The TCBRA value is transferred to TCDRA with the transfer timing set in TMDR1. The initial value of
TCBRA after a reset is FFFFh.
19.2.28

Timer Dead Time Data Register (TDDRA)

Address(es): MTU.TDDRA 0009 5216h
b15 b14
1 1
Value after reset:
Note: TDDRA must not be accessed in 8 bits; it should be accessed in 16 bits.
TDDRA is a 16-bit readable/writable register, used only in complementary PWM mode, that specify the MTU3.TCNT
and MTU4.TCNT counter offset value. In complementary PWM mode, when the MTU3.TCNT and MTU4.TCNT
counters are cleared and then restarted, the TDDRA value is loaded into the MTU3.TCNT counter and the count
operation starts. The initial value of TDDRA after a reset is FFFFh.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b13 b12 b11 b10
1 1 1 1
b13 b12 b11 b10
1 1 1 1
19. Multi-Function Timer Pulse Unit 3 (MTU3c)
b9 b8 b7 b6
1 1 1 1
b9 b8 b7 b6
1 1 1 1
b5 b4 b3 b2
1 1 1 1
b5 b4 b3 b2
1 1 1 1
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b1 b0
1 1
b1 b0
1 1